-> Good understanding of Fundamentals of Transistor and Circuit Theory -> Good understanding of the ASIC and FPGA design flow -> Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog -> Very good knowledge in verification methodologies. -> Expertise with TLM, OVM, UVM verification environment. -> Experience in using industry standard EDA tools for the front-end design and verification -> Strong knowledge on C, C++ -> Strong skills in using OOPS concepts with secure coding practices. ->
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Project InternMaven Silicon Mar 2013 - Sep 2013AHB2APB Bridge - Verification -
Vlsi - Digital Design/Verification Trainee Maven SiliconMaven Silicon Oct 2012 - Feb 2013Bengaluru Area, IndiaI cleared a interview and got a confirmation to start my training at Maven Silicon.I am trained on Digital Concepts, Verilog and System verilog.Basic knowledge of OVM and UVM methodology.
V P Education Details
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First Class -
Narayana Junior CollegeDistinction -
Sri Vidya High SchoolSsc
Frequently Asked Questions about V P
What is V P's role at the current company?
V P's current role is Actively looking for Full-time opportunity in ASIC/FPGA Design Verification Engineer.
What schools did V P attend?
V P attended Jawaharlal Nehru Technological University, Narayana Junior College, Sri Vidya High School.
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Vishal Patil
Pune1hotmail.com
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