-> Good understanding of Fundamentals of Transistor and Circuit Theory -> Good understanding of the ASIC and FPGA design flow -> Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog -> Very good knowledge in verification methodologies. -> Expertise with TLM, OVM, UVM verification environment. -> Experience in using industry standard EDA tools for the front-end design and verification -> Strong knowledge on C, C++ -> Strong skills in using OOPS concepts with secure coding practices. ->