Vasanth Kumar K Email & Phone Number

Hi I’m Vasanth Kumar , I am physical design and verification engineer (VLSI) . Trained with PD including Floorplanning, power-planning , multi-voltage designs, placement, CTS, and Routing, Static timing analysis , physical verification.Strong background in RTL-GDSII flow/methodology development, flow debug, enhancement on 3nm , 4nm ,14nm,28nm,45nm lower technologies.Should be capable of providing solutions to flow, tool, design setup elated issues .Strong TCL scripting knowledge regressing P&R flows.Familiar with sign-off issues (metal Drc, base Drc, lvs ,metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies.able to do timing closures also. Tools :ICC/ICC2 , Fusion compiler , Calibre , Tanner EDA, Primetime, design compiler .Projects : Physical Design Implementation on ORCA using 32nm Technology Node:In this project I worked on multi-voltage design with 55k+ Standard cells.Performed floor planning, voltage area creation, macro placement and place n route on design using industry standard tools.Resolved timing critical paths at placement and Post-CTS stages.Hence optimized it for proper timing closure. Overall Design contains 40 hard macros.Static Timing Analysis of Inter Integrated Circuit (ORCA): Pursued Static Timing Analysis of a functionally verified Routed Netlist of ORCA .design of32nm technology. In this project the set of constraints for timing analysis (.sdc) was developed and StaticTiming.Analysis (STA) was performed using Synopsys–Prime Time(PT).Captured various types of timing violations that can occur and fixing them by understanding the concepts.Router implementation on Fusion compiler : compile flows like initial map, logic opto , initial opto, initial drc implementation also done using FC. Design and Implementation of 3R robot for an industrial application using conveyors:Using Acrylic we have to first created 3R (3links) and then we are connecting that using motors(servo motors)for fabrication . For conveyors also we use 3D printing to be in and use that in project .

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  Physical Design Engineer

  Maven Silicon

  Sep 2023 - Present - Bengaluru, Karnataka, India

  From the institute I get the knowledge of physical design and verification engineer that includes ASIC design flow includes partitioning, floorplanning , placement , CTS, Routing, Static timing analysis , signoff and physical verification .