Vedant Kulkarni Email & Phone Number

Electrical Engineering Graduate Student at Arizona State University, specializing in Electronics and Mixed-Signal Circuit Design. With Bachelor’s in Electronics and Communication Engineering, I have gained vast skill set and knowledge encompassing Analog IC Design, Digital Systems Design, VLSI Design, EDA tools, Hardware Description Languages, Programming languages and Computational Software.To enhance my conceptual understanding of Analog IC and VLSI Design, I have worked on various projects including ASIC acceleration for GCNs (RTL to GDSII), designing of Standard Cell using 7nm FinFET, 4-bit Ripple Carry Fuller Adder Design, Two-Stage Miller Compensated Operational Amplifier, and Differential Amplifier using Active load. These projects enabled me to get hands-on experience in EDA tools like Cadence Virtuoso, Innovus, ModelSim, Synopsys DC, and Spectre. From Verification and Testing perspective, I devised test plans to verify VeriChip Design against provided specifications. Performed read/write operations using System Verilog on VeriChip registers such as ALU, Command, Version, Configuration, and Status. I formulated covergroups and coverpoints to ensure 100% code coverage in line, toggle, FSM and condition coverages using Synopsys Verdi. Overall, I am passionate about leveraging my skills and knowledge in Electrical Engineering to tackle real-world challenges. I am excited about the opportunities ahead and looking forward to contributing positively to any team or project I am a part of.