Hareesh Vemulachedu Email & Phone Number

Edinburgh, Scotland, United Kingdom

Singapore

SPICE Tech Lead for 40nm Tech nodes in GF across the fabs. Responsible for close to 50+ SPICE/PDK releases with a high KPI. Key member in GF's first successful Tech Txfer and created SOP for subsequent Tech Txfer.. Trained and coached new members in the area of SPICE Modeling.

Singapore

Member of Technical Staff working in the area of SPICE Modeling. SPICE Technical Lead and Project Management for 40nm programs.

Penang, Malaysia

Responsible for SPICE Model QA, enablement and design environment setup for circuit designers in advanced technology nodes like 14nm and 20nm.Master level expertise in Parameter extraction & QA tools - ProPlus, Keysight MBP and MQA. Data processing with PERL, VBA, JMP and other statistical software..

Penang, Malaysia

Responsible for SPICE Model QA, enablement and design environment setup for circuit designers in advanced technology nodes like 14nm and 20nm.Master level expertise in Parameter extraction & QA tools - ProPlus, Keysight MBP and MQA. Data processing with PERL, VBA, JMP and other statistical software..

Penang, Malaysia

Acting manager for the SPICE modeling group for a period of one month. Overseeing the activities of the group and project management.

Penang, Malaysia

Responsible for SPICE Model QA, enablement and design environment setup for circuit designers in advanced technology nodes like 14nm and 20nm.

Singapore

Responsible for the development and support of SPICE model libraries for MOSFET devices using BSIM, PSP and HSIM-HV models for the technology nodes ranging from 28nm to 0.18um for LOGIC, HV and MEMORY applications. It includes the characterization, parameter extraction, Model QA, developing Library syntax for different simulators and bench mark circuit Analysis. Passive device modeling using standard models and with Verilog-A implementation

Singapore

Responsible for the development and support of SPICE model libraries for MOSFET devices using BSIM, PSP and HSIM-HV models for the technology nodes ranging from 28nm to 0.18um for LOGIC, HV and MEMORY applications. It includes the characterization, parameter extraction, Model QA, developing Library syntax for different simulators and bench mark circuit Analysis. Passive device modeling using standard models and with Verilog-A implementation.

Worked as a project associate in the project funded by DST ( Department of science and technology ), an R&D wing connected to Govt. of India. In this project we demonstrated the novel use of Silicon as the biosensor which can be used in healthcare and food safety. * Hareesh Vemulachedu et al "Miniaturization of EISCAP sensor for triglyceride detection, Jour. Materials Science: Materials in Medicine, 2008, doi: 10.1007/s10856-008-3534-y" * Renny Edwin Fernandez, Hareesh Vemulachedu, Enakshi Bhattacharya and Anju Chadha "Comparison of a Potentiometric and Micromechanical Triglyceride Biosensor, Biosensors and Bioelectronics, Volume 24, Issue 5, 1 January 2009, Pages 1276-1280."