Vilas P Nakade Email & Phone Number

# 20 years of technical and management experience in VLSI industry# Hands on experience of RF & Analog Mixed Signal Layout design# Responsibilities: team management, project management, project planning and execution, milestone tracking, quality checks and final release# Involved in customer interaction, resource planning, recruitment process, technical interview and mentoring# Hands on layout work experience on cutting-edge, deep sub-micron, FinFet & planner and multi pattern technology like 5nm, 7nm, 10nm, 14nm, 16nm, 28nm, 65nm, 90nm etc # Have worked on various DDR PHY like DDR43, DDR54, LPDDR54 architecture layout planning, execution and releases# Track record of first pass silicon proven design from layout placement to GDS release# Hands on experience of layout of RF blocks like LNS, LDOs, Band gap, Buck and power management blocks, amplifier etc.# Hands on experience of analog blocks like sigma-delta ADC, SAR-ADC , DAC, LDO, Charge pump, Band gap, Buck and power management blocks, PGA, ET, amplifier etc.# Have worked on silicon proven full chips like audio codec (4 tape outs), Ethernet modem, standalone IP’s, metal fixing and Focused Ion Beam (FIB) for the chip. # Worked on multi-client project where 4 companies was involved. It was DDR (T12nm) project# Played a significant role in IO library layout and releases like glitch filter, slew controlled buffers. Also worked on post layout verification, spice simulations of RC extracted netlist.# Worked on multiple projects simultaneously with different clients# Sound knowledge of analog/RF layout concepts like layout matching, shielding, latch-up & ESD requirement, DFM, EM & IR analysis, current density requirement, power mesh etc.# Sound knowledge of PhyV verification like DRC, LVS, ERC, Antenna, DFM. # Worked on PERC verification and ESD requirement, boundary/abutment methodology and quality checks # Played a significant role and created methodology and approach to reduce layout turnaround time, improve quality, checks to catch defects in release data# Received appreciation and spot bonus at multiple occasions for IP releases with zero defect, first pass silicon proven releases & PPA# Good communication skill, hardworking, effective team player. eager to learn new things and like to face challenges.# Tools worked on: Cadence Virtuoso layout editor, Custom designer/compiler, Schematic Composer, PV, Assura, Calibre, Hercules verification tools# Scripting Languages: SKILL, Perl# Have work experience of top semiconductor companies: Synopsys, Texas Instruments, Qualcomm, AMD, SCL

Listed skills include Mixed Signal, Asic, Analog, Verilog, and 17 others.