Pcell development, Analog design flow automation ,design migration platform development ,PDK QA/ enablement, layout automation utility development.

ASIC Development Engineering-Mixed Signal IP Design and Automation•PDKQA Methodology Development Framework for multiple PDKs •Design Porting Methodology Development and Automation for Advance Nodes (7nm, 5nm)•Standard Cells QA framework and Solving Challenges related to CDF and Netlisting.•In In-house performance analysis methodology development and dashboard of the Standard cells library in terms of Power and Delay across multiple flavours.•Timing critical liberty generation methodology for AMS block. •Power Domain Checks•Methodology Development in Skill for Productivity enhancement.\•Enabling PDKS and project environmentScripting using Perl, Shell and Python.•Debugging Tools and Environment related issues across multiple Vendors•Tools benchmarking and enablement•Tools: Cadence Virtuoso, Calibre PV tools, XRC, StarRC, PrimeTime,Xcelium•Simulators benchmarking•Simulation tools: Spectre, AFS, Finesim, DC compiler support•Supporting designs teams in flow, automation and CAD flows activities.•Engaging with EDA vendors for new tool evaluations, new feature and training plans for design community.•Internal CAD tool development.•Mentoring interns for their internship projects and their projects.Technology worked 28,16nm,7nm,5nm

CAD Engineering Creating Test Automation environment and CI- CD development using jenkinsCreated a Automated Reporting platform for Sanity Test of IP Verification to ensure the performance and continuous monitoring of environment and reduce manual running of test's reporting, reducing design bandwidth.

Course work in:Digital Design,Digital CMOS VLSI Design,Low power VLSI design,DSP, Embedded Systems , Physical Design,STA concepts,Virtuoso labs , Verilog.Lab Teaching as an Teaching associate :VLSI Design Digital DesignSignals and SystemsAnalog Electronics It includes conducting Lab session , Design lab experiments, project assignments.