Scenior Technical Manager with 8+ years in Mixed-Signal Modeling and Verification at MediaTek Inc.Mixed-signal modeling and verification engineer for PMIC and related IPs. Specialist of analog circuit behavior modeling, digital/analog design verification (RTL simulation) and co-verification platform planning.Analog circuit behavior modeling of PMIC related IPs with real-valued Verilog-DVerilog IP level whole block or down to dedicated circuit level modelingVerilog netlist with UPF providing for power-aware simulationCo-simulation (VCS) for analog behavior model and digital designPMIC cross-chip model and simulation platform building for different AP/SOC applicationPMIC and AP/SOC co-simulation integration, environment setting and debuggingLed PMIC verification effort of MSV team, mentored junior engineers