Weiwei Jin Email & Phone Number

Beijing, China

中国 北京市区

1 SoC chip using TSMC 28hpc+ process: huge block (70millions+ gate count) implementation with ICC2/Calibre/Voltus；build N2G backend flow, including floor planning, power planning, P&R, timing signoff, power/rail analysis, PV/DFMTapeout 2 SoC chip using GF 28nm SLP process: blocks implementation with ICC2/Innovus/Calibre/VoltusTapeout 1 SoC chip using TSMC 40nm LP process: blocks implementation with ICC/Calibre/EPSTapeout 4 SoC chips using TSMC 65nm LP process: lead to implement the whole chip with ICC/Calibre/EPS

Back End:MPEG2/AVS SD Decoder SoC chip P&R and tapeout:(2011.03-2011.06) run placement for TOP in ICC; run CTS and routing for TOP in Encounter; tapeout with TSMC CLN90G process.H264/MPEG2/AVS HD Decoder SoC chip ECO flow:(2011.08-2011.09) run ECO flow for whole chip in Encounter.Front End:MPEG2/AVS SD decoder core verification and FPGA test:(2010.10 – 2011.02) establish testbench for video decoder core to enhance function coverage; run code coverage simulation with VCS; write DDR obfuscator model with Perl.H264/MPEG2/AVS HD decoder core firmware optimization:(2011.07-2012.03) modify decoder core firmware to improve decode performace and communication with host CPU.

Front End:Interfaces Design for Media Processor: (2007.08 – 2007.12) Establish a behavioral model: model the protocols of interfaces between media processing core and SDRAM controller, Demux unit and video/audio players; run behavioral simulation integrating the interfaces with the media processing core which is implemented by PLI models. RTL coding, verification and synthesis: (2008.01-2008.05) RTL coding for stream and player interfaces; integrate interfaces, AHB slave bus and ARM core master to run simulation and verification; synthesize the interfaces and AHB slave bus with Faraday 0.13um library at 266MHz for ARM core clock domain and 133MHz for SDRAM clock domain. Hardware Acceleration for Multi-mode Media Processor: (2008.06 – 2008.12) DCT/IDCT block: RTL design to implement transformed data input/output and row/column conversion; whole block verification and synthesis;Motion compensation block and Intra Prediction block:RTL design, verification and synthesis. Video Graphic Processing Chip Design: (2009.07-2010.01)VLC Decoder for H264 and AVS: (2010.02-2010.09)Back End:DDR2 Controller synthesis and P&R: (2009.01-2009.06) run synthesis in DC and P&R in Astro; 333MHz with TSMC 0.13um process.

Back End: (2005.07 –2006.04)Physical verification including DRC/LVS/ERC/ANTENNA/Power AnalysisR2G back-end chip design: process of 0.25um EMBFLASH 2p5m 2.5V/3.3V/HV; synthesize, floorplan, place&route; Front End: (2006.05 – 2007.07)DFT modules of 0.18 and 0.25 um eFlash: RTL code and testbench design; create compiler for DFT modules of different eFlash configurations with Perl language.BIST/R modules for 65 and 90 nm eDRAM: testbench creation and test patterns generation.

Master, Microelectronics, Top 5/30

Activities and Societies: In graduate school, I was appointed as the vice-president of graduate student union and organized some academic.

Bs, Electronic Engineer, Top 1/30

Activities and Societies: In undergraduate school, I got several college's first-class scholarships and I was entitled as "First-rank.