• Design lead for LPDDR5 Emerging Memory SDRAM• Die floor planning • Defining headcount needs and schedule• Project Management• Task assigning for up to 40 design and 45 layout • Preliminary Planning for LPDDR5 Emerging Technology SDRAM Design• Defining optimal die architecture• Assessing performance capabilities ● 16Gb DDR4 Array Design Lead• Performance analysis of speed and IDD specifications• Optimized Column redundancy for die size and predicted yields• Directing device reliability analysis, including CHC, NBTI, and CHISEL degradation• Determining and placing appropriate supply decoupling cap allocations

● Lead Designer for LPDDR5 Emerging Technology SDRAM ● Lead Designer for LPDDR4 Emerging Technology SDRAM ● Optimized array architecture to meet package constraints for 20nm 6Gb LPDDR4 SDRAM ● Lead Designer for high volume 8Gb LPDDR4 (20nm node) SDRAM

● Lead Array designer for 2Gb DDR3 (30nm node) SDRAM● Conceived and implemented first TRR circuit for DDR4 SDRAM designs ● Lead Designer for 2Gb DDR3 (50nm node) SDR● Executed fullchip CMOS Reliability analysis CHC, CHISEL, & NBTI degradation

● Lead Designer for high volume 256Mb 130nm DDR SDRAM● Designed DRAM Row and Column redundancy planes ● Responsible for cell floor-planning process, placement and signal route optimization● Developed antifuse repair logic scheme for 128Mb DDR SDRAM ● Ran circuit simulations using standard industry simulators such as SPICE and VERILOG

● Initial Si troubleshooting to provide revision fixes for critical 64Mb SDRAM functional failures● Optimized wafer level testing to balance array repair usage and backend yields; required in depth analysis and understanding of cell failure mechanisms ● Yield Enhancement for 1Meg, 4Meg, and 16Meg Fast page and EDO DRAM high volume products ● Collaborated with Probe, Assembly, Test, and Process Integration groups to optimize manufacturability of a product● Microprobing of internal signals and power busses on Si wafers