Contracting position in post silicon validation for Microsoft Azure ARM base server processor. Focusing on RAS, security and memory controller areas.

Led Debug efforts to root cause emulation test execution failures on Synopsys Zebu Emulation platform for Intel Server processors and other high performance computing processors. Main duties were preforming initial debug followed by providing directions for team members to collaborate with RTL design, Firmware and BIOS development teams to root cause failuresDeveloped shell scripts and python scripts to automate Firmware and BIOS generations process. Greatly reduced the junior engineer's reliance on the experienced Firmware and BIOS team members to generate these emulation collaterals correctly during revision updatesDebugged In house Emulation Transactors issues mostly on the synthesizable RTL sideImproved Emulation Transactors efficiency by better packetizing and avoid redundant packets communicationsCollborate with Emulation Platform team to migrate software simulation BFM to emualtion transactor working on the synthesizable RTL side.

RTL design for DDR memory controller data paths and DFX features.RTL design and verification for various parts of enterprise SSD controllers and SoC products. From NVMe command processing to power regulation, quiescent detection logic for power saving to retrofitting older designs for high speed synthesis. Synthesize cut down versions of SSD SoC designs onto FPGA emulation boards for verification and path finding projects to explore new featuresExposure to Embedded System Firmware development for ARM cores

Partition and synthesize SoC designs onto multiple FPGA devices ICE platforms.Developed FPGA codes and sometimes microcontroller code to provide stimulus to the SoC DUTDefined ICE platform coverage and led debug efforts to root cause execution failures.Worked with BIOS team to adapt a cut down BIOS to allow a SoC product with Atom core to boot Windows and Linux on the ICE platform. Uncovered a RTL issue and BIOS provided workaround before A0 silicon arrival.

Post silicon verification for SoC network processors.Developed bare bone drivers in C for execution of verification tests which stressed the packets processing of the processors to the limit and with accurate self checking capability.Developed FPGA code for I2C, SPI to work with microprocessors to test DUT functionalities.Developed a bare bone Windows NDIS network driver and Linux network driver for an Infinband adapter proof of concept project with shared code base for packets processing and basic IOCTL functionalities.

Led small teams to develop Wireless modem Firmware, Windows and Linux OS device drivers. As individual contributor on FPGA/CPLD logic between microprocessor and DSP chips.