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William Binder Email & Phone Number

Principal Static Timing Analysis and Methodology Support Engineer at NVIDIA at NVIDIA
Location: Apex, North Carolina, United States 8 work roles 2 schools
1 work email found @nvidia.com LinkedIn matched
✓ Verified Jun 2026 4 data sources Profile completeness 100%

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Work email w****@nvidia.com
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Current company
NVIDIA
Role
Principal Static Timing Analysis and Methodology Support Engineer at NVIDIA
Location
Apex, North Carolina, United States
Company size
41500 employees

Who is William Binder? Overview

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William Binder is listed as Principal Static Timing Analysis and Methodology Support Engineer at NVIDIA at NVIDIA, a company with 41500 employees, based in Apex, North Carolina, United States. AeroLeads shows a work email signal at nvidia.com and a matched LinkedIn profile for William Binder.

William Binder previously worked as Principal Static Timing Analysis and Methodology Support Engineer at Nvidia and DDR STA Lead - Senior Staff Engineer at Qualcomm. William Binder holds Bs, Electrical And Computer Engineering from Worcester Polytechnic Institute.

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Email format at NVIDIA

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{first_initial}{last}@nvidia.com
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Profile bio

About William Binder

Looking to obtain a technical leadership position in hardware design back end processes, with an emphasis on static timing closure and/or timing analysis methodology development.20 years of experience in static timing closure, tool/methodology development, VLSI/ASIC design, and functional verification. Knowledge of IBM, Synopsis, and Cadence EDA tools. Knowledge of Perl, Tcl/TK, Shell Scripting, LEF/DEF, UPF, and Verilog/VHDL. Rudimentary knowledge of Python. Knowledge of Windows, Unix, and MS Office tools (Word, Excel, PowerPoint), etc.Experience leading and working with local, cross-site, and international teams. Experience presenting technical material to various audiences, ranging from new hires to upper level management.Specialties: Static timing closure (including timing constraint development, ECO writing and implementing, derating, extrapolation and interpolation, deterministic and statistical timing closure, power reduction, critical path SPICE analysis, etc.)Tool/methodology development, particularly as it pertains to static timing closure

Listed skills include Static Timing Analysis, Asic, Tcl, Perl, and 45 others.

Current workplace

William Binder's current company

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NVIDIA
Nvidia
Principal Static Timing Analysis and Methodology Support Engineer at NVIDIA
Apex, NC, US
Website
nvidia.com
Employees
41500
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8 roles

William Binder work experience

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Role listed

Nvidia

Apex, NC, US

Principal Static Timing Analysis And Methodology Support Engineer

Current
Nvidia

Santa Clara, CA, US

Sep 2018 - Present

Ddr Sta Lead - Senior Staff Engineer

Qualcomm

San Diego, CA, US

DDR Subsystem Timing Lead in Qualcomm Datacenter Technology group, which delivered the Qualcomm Centriq 2400 to market - the world's first 10nm server processor.Owned static timing closure of large, complex DDR subsystems (2M - 5M instances) in advanced technology nodes through 14 nm, 10nm, and beyond. Wrote and maintained constraints for multiple.

May 2016 - Sep 2018

Staff Engineer

Qualcomm

San Diego, CA, US

Performed timing closure duties for large, complex, low power mobile and server CPU SoC designs spanning 28, 20, 16, and 14nm technology nodes.Owned static timing closure of large, complex DDR subsystem operating at speeds up to DDR4-2667 Mbps. Wrote and maintained timing constraints, worked with designers and front end synthesis team on design changes.

Dec 2012 - May 2016

Advisory Engineer

Ibm

Armonk, New York, NY, US

Static Timing Engineer in World-Wide ASIC Design Center.Performed technical leadership and lead timing closure duties for many large and complex ASIC designs. Designs spanned 120, 90, 65, 45, and 32 nm technologies. Consulted with customers, drove tool and methodology choices, and led back end design team to design closure from early analysis and floor.

Jun 2006 - Dec 2012

Staff Engineer

Ibm

Armonk, New York, NY, US

Static Timing Engineer in Network Processor Development and POWER Microprocessor DevelopmentOwned timing closure responsibilities for several IBM Network Processor designs. Wrote timing constraints, reported status to management, and worked with logic designers, synthesis resources, and back end layout team to ensure a design that met all timing.

Jun 2001 - Jun 2006

Engineer

Ibm

Armonk, New York, NY, US

FPGA Designer and Functional Verification Engineer in Network Processor Development.Designed and implemented FPGA designs to aid in emulation of IBM Network Processor IP.Performed functional verification for several units of IBM Network Processor. Assumed ownership of a large suite of C/C++ golden model code for embedded processor complex and tree search.

Apr 2000 - Jun 2001

Electrical Engineer I

Raytheon

Arlington, VA, US

FPGA Designer for government satellite communications projects.Architected, designed, coded, verified, and integrated FPGAs.Secret Level US Government security clearance held.

May 1998 - Mar 2000
Team & coworkers

Colleagues at NVIDIA

Other employees you can reach at nvidia.com. View company contacts for 41500 employees →

SR Shridhar Rasal Shridhar Rasal Colleague at NvidiaPune, Maharashtra, India, India View → PK Prasanna Karmalkar Prasanna Karmalkar Colleague at NvidiaPune, Maharashtra, India, India View → PH Patrik Hadorn Patrik Hadorn Colleague at NvidiaZurich, Switzerland, Switzerland View → MM Matt Mcanally Matt Mcanally Colleague at NvidiaAtlanta, Georgia, United States, United States View → LG Lark Gordon Lark Gordon Colleague at NvidiaRaleigh-Durham-Chapel Hill Area, United States View → SL Sivan Lifschitz Katz Sivan Lifschitz Katz Colleague at NvidiaIsrael, Israel View → PP Priya Pandian Priya Pandian Colleague at NvidiaSan Jose, California, United States, United States View → HL Haihua(Patricia) Li Haihua(Patricia) Li Colleague at NvidiaSanta Clara, California, United States, United States View → SP Sergio Paiagua Sergio Paiagua Colleague at NvidiaSan Francisco Bay Area, United States View → RD Rohan Dhekane Rohan Dhekane Colleague at NvidiaSan Jose, California, United States, United States View →
2 education records

William Binder education

Bs, Electrical And Computer Engineering

Worcester Polytechnic Institute

Education record

Southington High School
FAQ

Frequently asked questions about William Binder

Quick answers generated from the profile data available on this page.

What company does William Binder work for?

William Binder works for NVIDIA.

What is William Binder's role at NVIDIA?

William Binder is listed as Principal Static Timing Analysis and Methodology Support Engineer at NVIDIA at NVIDIA.

What is William Binder's email address?

AeroLeads has found 1 work email signal at @nvidia.com for William Binder at NVIDIA.

Where is William Binder based?

William Binder is based in Apex, North Carolina, United States while working with NVIDIA.

What companies has William Binder worked for?

William Binder has worked for Nvidia, Qualcomm, Ibm, and Raytheon.

Who are William Binder's colleagues at NVIDIA?

William Binder's colleagues at NVIDIA include Shridhar Rasal, Prasanna Karmalkar, Patrik Hadorn, Matt Mcanally, and Lark Gordon.

How can I contact William Binder?

You can use AeroLeads to view verified contact signals for William Binder at NVIDIA, including work email, phone, and LinkedIn data when available.

What schools did William Binder attend?

William Binder holds Bs, Electrical And Computer Engineering from Worcester Polytechnic Institute.

What skills is William Binder known for?

William Binder is listed with skills including Static Timing Analysis, Asic, Tcl, Perl, Eda, Functional Verification, Verilog, and Soc.

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