William Schilp Email & Phone Number

Burlington, Ma

Leading the development of the VHDL-AMS compiled code simulator.

Senior member of the R&D team of a startup company to deign and implement a highly parallelized, multi-threaded circuit timing tool. Responsibilities included analyzing various parts of the code for single and multi-threaded performance and implementing enhancements to performance. Debugging the code base including finding and fixing race conditions and deadlocks. Some projects of note: - Designed and implemented a parallel algorithm with minimal locking to store circuit node names in a modified radix tree type database. The algorithm had to store multiple names in parallel (multi-threaded) and also support multiple parallel searches of the database (multi-threaded). - Designed and implemented a parallel algorithm to elaborate a circuit with minimal locking. The algorithm scaled linearly with the number of CPU’s (up to 16, the largest server we had).

Various duties in the design, development and maintenance of a large line of software products (> 6MLOC) to assist hardware designers (such as Intel, Motorola, AMD, etc). The company is multi-national, and as such part of my duties have included coordinating development between groups located in Noida India, San Jose CA , Chicago IL and Chelmsford MA.

Ph.D., Computer Science

Activities and Societies: Scuba club

Ms, Computer Engineering

Activities and Societies: Scuba Club

Bs, Computer Engineering

Activities and Societies: Scuba Club, Tau Beta Pi