Continuous Integration Engineer For Fpga Development
Lead Designer, Continuous Integration Engineer for FPGA IP Development- Increased build turns from 1 to 20 per day by designing/implementing continuous delivery system for 400 FPGA IP and 200GB code base of C++, Verilog, VHDL, TCL, Java, data and test files. - Reduced build time by 90% (240 to 20 minutes) by designing/implementing a new make Windows/Linux process using a cloud-based GNU make compatible system. The non-recursive, data-driven makefiles used subroutine-like calls to eliminate user created makefile rules and enhance maintainability and flexibility.- Streamlined/standardized development process by creating procedures and Perl/Python tools for versioning, verification, formatting source code, and maintaining IP specifications and data. - Eliminated duplicate data entry of marketing/specification data by generating data files at build time using Perl and TCL from various MySQL, MongoDB, JSON and XML databases, Excel, source code and data files. - Automated Perforce developer process flows, enforced SCM rules and integrated with CI system by developing Perl scripts utilizing Perforce API.