Responsible for Operations and Inventory for Datacenter and AI Group (DCAI) Lab Infrastructure in India, Mexico, China and the US in support of Platform Validation

Solution Architect in Corporate Remediation Group that developed database architecture to track Pre-Production Hardware (Boards/Systems and Silicon). This also included developing new capability in HSD-ES to link Microcode CPUID to intel Finished Goods.

Developed a innovative method of tracking prototype Phone and Tablet devices using RFID and I2C technology. IPTrak utilizes the Cloud (Ruby on Rails) and RFID and I2C technology in a novel way for Phone and Tablet hardware to be managed remotely for the purpose of identifying configurations, maintaining reworks and tracking location. Developed the mobile application interface to work on iOS, Android and Windows OS devices.

Managed the Experience, Power and Performance Lab (ePnP) within the Mobile Communication Group (MCG) responsible for optimizing the Power and Performance trade-off on Intel Platform Systems.Leading the development of Worldwide MGC Lab Infastructure (China, India, US, Taiwan, Malaysia) in order to support the various teams working on new MCG initiatives. Responsibilities include working with the following teams:1) Intel Corporate Service team on negotiation of physical space available for Lab Conversion.2) Intel Finance to forecast Capital budget needs for lab build out and lab equipment.3) Supplier/Vendors to negotiate pricing and delivery on lab equipment and furniture.

Manage a team of Mechanical and Electrical Engineers responsible for performing CPU Thermal and Power Validation. Team is an expert in the area of CPU Thermal and Power Validation and Platform enabling. Also specialize in analysis of package thermal resistance and thermal and power reliability. Extensive background in fab copper dual damascene process.

Point of contact for Fab and Assembly/Test organizations focused on addressing Power/Thermal/Mechanical related excursions. Expertise in Thermal Diode, Thermal Packaging and Thermal/Power Mapping.

Responsible for bringing up Copper Electroplating process on Novellus Sabre equipment at Greenfield Site in Rio Rancho, New Mexico (Fab 11X). Experience working with Portland Technology Development (PTD) as Seed Engineer with responsibility of transferring 1260 process to Fab 11X.

Experience in wafer handling, robotics and new product development. Original Team Member on Sabre and SabrexT Copper Electroplating System Development. Utilized Pro/E for 3D modeling and design of components and systems.

-Designed and managed semiconductor equipment installation at LSI Logic, Gresham, OR campus. Areas of design included DI water, process gas, chemical, process cooling water and chemical drain systems. Responsibilities included creating an Acess database for the design specifications. -Project scheduling, design, installation and management of mechanical systems for new Hyundai/Hynix Semiconductor facility in Eugene, OR. Areas of responsibilities included design of DI water, process gases, chemicals, process cooling water and chemical drain systems.