Enhance system security with new processor and cache micro-architectures:• Defense control flow hijacking with hardware managed tagged memory.• Avoid cache side-channel attacks with new cache architectures.• Develope a fast cache model for fast cache side-channel attack/defense researches.• Evluating the vulnerabilities of a hardware system using a systematic test suite.

The lowRISC project: An open-source SoC hardware platform using the 64-bit RISC-V ISA.Working on the hardware side of the lowRISC SoC, from the core pipeline to IO devices. Hardware lead of its first four releases:• Added tagged memory support to Rocket SoC (L1 D$, L2 and tag cache).• Added memory mapped IO support to Rocket core.• Untethered Rocket chip SoC.• Booted a RISC-V Linux on the untethered Rocket chip using KC705 and Nexys4-DDR boards.

EPSRC Globally Asynchronous Elastic Logic Synthesis (GAELS) project.Parsing large-scale Verilog RTL design using Bison+Flex.Proposed a new signal-level data-flow graph to highlight control/data relations.Automatic controller extraction.Automatic data path extraction.Preliminary system partition using module interface identification.

Designed and implemented asynchronous spatial division multiplexing (SDM) routers for asynchronous on-chip networks.Designed and implemented the rst asynchronous scheduler for general three-stage Clos networks.Designed and implemented a high-speed asynchronous wormhole router for asynchronous on-chip networks.Proposed an adaptive stocahstic routing algorithm for fault-tolerant on-chip networks.

Courses demonstrated:COMP20252 Mobile SystemsCOMP20051 Operating SystemsCOMP20241 VLSI System DesignCOMP10031 Fundamentals of Computer ArchitectureCOMP10242 Microcontrollers

Wrote test scripts for commands of a linux operational system on a virtual machine.

Implemented an ATSC demodulator in three VIRTEX-4 FPGAs.Designed a symbol timing recovery module and a programmer scanner for a DVB-T demodulator chipset. Implemented the whole DVB-T system in one VIRTEX-II FPGA.Designed a common scrambling algorithm (CSA) decoder, a host adapter, an SDIO interface, a CF interface and a PCI slave interface for a DVB-H demodulator chipset.Designed a baseband-MAC interface, an APB register controller, several decryption modules for a WLAN 802.11g/b network card (supported by Beijing Municipal Commission of Edu. D0304004040111). Implemented the whole baseband in one VIRTEX-II FPGA.