Yash Vardhan Email & Phone Number

Toronto, Ontario, Canada

- Built up hands on expertise of automated layout place and route tools and flows (ICC2). Using those tools, completed several iterations of the NOC layout, ultimately delivering LVS/DRC clean, timing converged NOC layout.- Leveraged ICC2 skills and contributed to PE layout and delivery of the POD layout. Played a key role in resolving pin placement issues.- Led numerous ECOs internal to the datapath using cadence virtuoso and led layout implementation data path sub-blocks which were added to the PE Datapath module.- Played a lead role in resolving Synopsys ICC2 and Cadence Virtuoso interaction issues including resolution of paratic extraction and integration issues.

Montreal, Quebec, Canada

- Design Mask Layout for Analog and Digital Integrated Circuits: IC components, libraries of standard cells, high density silicon IP components for low-power System-on-Chip(SoC).- Design/Analysis/Verification of floor plan for IC solutions: Voltage Regulators virtual components and top level circuits using EDA tools at different process nodes:0.18um (TSMC), 45nm (TSMC),22nm (GF), 22nm (TSMC) - Knowledge of different silicon technologies: Bulk CMOS (e-flash, Ultra Low Power etc), FD-SOI, FinFET.

Toronto, Ontario, Canada

- Courses undertaken : Foundations of Project Management & Leading Projects in Organizations- Handled the course portal. - Supervised timely announcements, examinations and any in-course conflict. - Evaluating assignments and tests.

Master Of Engineering - Meng, Electrical And Electronics Engineering, 3.8/4

Bachelor Of Technology, Electrical, Electronics And Communications Engineering, 9.12/10 (First Division)