Yong Liu, Ph.D Email and Phone Number
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INDUSTRIAL ENGINEERING AND TECHNOLOGY DEVELOPMENT (1998-Present):FEOL/BEOL Semiconductor Process, Integration and Device R&D & Engineering for RF/digital CMOS, NOR/NAND flash memory cells, Si and Ge photonics (VOA, PIN/APD photo-detectors etc), GaN/InGaN, AlGaInP/GaAs MQW micro LED imager. Advanced e-test/yield analysis for semiconductor IC HVM. Device Characterization. Team Leadership and Management, Technology Development Program Management,Engineering and R&D Laboratory Management.__________________________________________SCIENTIFIC RESEARCH AREAS (Before 1998):Laser Spectroscopy (M.S. Degree). Laser Uranium Isotope Separation via CRISLA method (University Faculty). Chemical Reaction Dynamics on Silicon, Plasma Etch Chemistry of Silicon, Semiconductor Surface Science (Ph.D Degree). Electron-Molecule and Ion-Molecule Reactions (Research Fellow). Atom-Resolved Scanning Tunneling Microscopy of Si(111), Si(100) and GaAs(100)-2X4 Surfaces (Staff Research Scientist, UC San Diego).__________________________________________SELECTED PUBLICATIONS:1. Semiconductor Thermal Processing:http://www.electrochem.org/dl/ma/203/pdfs/0884.pdf2. Device Physics & Characterization:https://iopscience.iop.org/article/10.1149/1.32044043. Atom-Resolved Silicon Surface Science:http://www.sciencemag.org/cgi/content/abstract/276/5319/16814. Atom-Resolved GaAs Surface Science:http://focus.aps.org/story/v2/st3https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.81.413Expertise: [1] Si, Ge, GaN/InGaN, GaAs, AlGaInP, RTP, thin-film, diffusion, PECVD, PVD, plasma/RIE etch, RIE, fusion bonding, laser anneal, FEOL, MOSFET, NOR/NAND flash, e-Test, ATE, SPC. [2] UHV, TPD, STM, AES, LEED, XRF, SIMS, XPS/ESCA, TEM, SEM, EDS, FTIR & Raman spectroscopy, 4-point probe, spectroscopic ellipsometry, SPV, Quantox (COCOS). [3] Mass spectrometry QMS, Ion-trap TOF MS, Ion mobility spectrometry, Ion-molecule reactions, Electron attachment, Laser spectroscopy, Laser chemistry, Laser uranium isotope separation. [4] JMP, DataPower, C++, MatLab, Visual Basic, FORTRAN, MS ACCESS, AutoCAD, Numerical Modeling.
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Process Integration DevelopmentIntel Corporation Jun 2024 - PresentSanta Clara, California, Us
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Founder & Chief ScientistHelm Scientific Laboratory Feb 2023 - May 2024Laser spectroscopy and instrumentation. Design, manufacture and market low-cost, high-quality 532 nm laser Raman/fluorescence spectrometers for education, academic and industrial labs. Raman/fluorescence spectral analytical services.Advanced electric & optical parametric characterization service (IV, LIV, CV, EL, PL, transient, pulsed) of semiconductor transistors, devices & test structures on wafers & chips. -
Director, Semiconductor Development & EngineeringOstendo Technologies Jul 2016 - Jan 2023Carlsbad, Ca, UsHands-on advanced III-V semiconductor MQW micro LED process, device and integration R&D and engineering. Micro LED image chip design, validation and optimization for augmented reality (AR) applications.Lead an Engineering Department of mask design, integration, photo lithography, thin-films deposition, dry/wet etch, metal plating, wafer bonding, laser processing and E-test. Oversee µLED imager chip’s low-volume manufacture and engineering activities. Propose and execute technology development roadmaps, plans and programs. Outline program key milestones, objectives and timelines. Organize and lead inter-department engineering project teams. Allocate resources to projects. Regularly update program status to company executives. Hire and advice talents. Review the performance of direct reposts. -
Process And Device Research & DevelopmentTowerjazz Semiconductor Dec 2014 - Jul 2016Migdal Haemek, Israel, IlDevelop advanced CMOS processes (etch, photolithography, Si/SiO2/SiNx/polyimide/metal thin-film growths) and devices for infrared image sensors and MEMS. -
R&D ManagerRec Silicon Jun 2012 - Sep 2014Moses Lake, Washington, UsLead and manage a research team consisting of project managers, scientists and supporting staffs. Reporting to R&D Executive of REC Si, plan and execute research projects in adherence to company R&D roadmap. Participate in formulating company R&D Roadmap and maintain close contact with the R&D management team within REC Silicon Company. Manage all aspects of the daily research activities and operations of the R&D laboratory with multi-million dollar annual budget. Develop and empower each group member to effectively reach short-term and long-term goals. Give scientific or technical advice and guidance to project managers, scientists and supporting staffs. Review research progresses and set technical directions. Lead, plan and execute advanced experimental researches into silicon (Si) etch and deposition processes under high-temperature, high-presssure or catalyzed conditions. Conduct advanced theoretical modeling and experiment into the processes and fundamental chemistry of semiconductor-grade or solar-grade silicon. These works involve the extensive use of advanced spectroscopic, mass spectrometric, and surface diagnostic instrumentation such as Micro-Raman, FTIR, XRF, XRD, HR-XPS/ESCA, AES, SEM/EDS, TPD-MS and GC. -
Principal EngineerKotura, Inc. (Acquired By Mellanox In 2013) Apr 2010 - Jun 2012Leading Diffusion/Thin Film and Wet Process engineering for silicon and germanium-based opto-electronic device technology development, including plasma-enhaced chemical vapor deposition (PECVD), physical vapor deposition (PVD), furnace diffusion/oxidation, rapid thermal processing (RTP), ion implant and all wet bench processes. Design, fabricate and characterize electronic test structures for fab processes/materials development, process monitoring and device development. Germanium crystalline bulk and interface defect reduction for device leakage suppression.
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Principal Member Of Technical StaffInnovative Silicon (Acquired By Micron In 2010) Jun 2008 - Apr 20101. Advanced methodology development of memory cell and device characterization (IV, CV, RF transient).2. Device & process optimization via parametric test, device layout and silicon metrology. 3. Scribe-line test structure development, test code development and automation.4. Transient leakage pathways/mechanisms investigation via high-speed real-time monitoring of memory cell floating-body potential.5. Theoretical and numerical modeling of MOS device/memory cell leakage mechanisms. 6. Technical paper writing and publishing.In-depth investigation into the fundamental device physics of the novel zero-capacitor random access memory (Z-RAM, 1T0C structure) by means of advanced DC and AC device parametric characterization methodologies. The particular focus is on real-time ultra-fast transient floating body electronic processes (nano second regime) related to cell operation and data retention, e.g. carrier generation/recombination at defects inside junctions and at interface traps of a single Z-RAM cell. Understanding of these processes during memory cell WRITE, READ and RETENTION operations is critical for the success of Z-RAM technology development.
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Nand Jdp Device Lab Manager, Senior Device/Staff Process Technology Development EngineerIntel Corp May 2004 - Jun 2008Santa Clara, California, UsAs a Rapid Thermal Process (RTP) expert in D2 Fab in charge of ultra-thin gate dielectrics, oxide nitridation, re-oxidation and source/drain and tip (extension) anneal modules. Developed rapid thermal processes for 90, 65 and 45 nm NOR flash memory nodes and 90 nm logic node. Served as a technical member in CMOS and Cell Focus Teams for multiple generations' flash memory technology development as well as in Device Parametric TMI (Target, Maintain and Improve) Team of D2 chipset production. Provided direct engineering guidance to the high volume manufacture (HVM) of Intel's chipset, NOR flash memory and other logic products through the RTP modules. Carried out processing technology transfer from D2 to Intel's production Fabs. Established a multi-million-dollar and state-of-the-art Device Laboratory from scratch for the Intel-Micron NAND Joint Development Project. By evaluating and qualifying instrument and hardware units from top-tier vendors, constructed three first-class wafer-level device parametric test systems to meet the challenging and evolving device R&D need. Managed all aspects of daily lab operation/activity. Developed powerful automated parametric test software packages for NAND device characterization. Carried out in-depth flash device physics investigation and process issue segmentation for the 70, 50, 3x nm NAND flash memory technology development.
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Principal Scientist & Selox Project ManagerAxcelis Technologies Jun 2000 - Oct 2003Beverly, Ma, UsSELOX, namely selective oxidation, is a unique high-temperature oxidation method that uses proper percentage of water steam in hydrogen ambient to repair metal gate stack edge damages from etch and ion implant. It selectively oxidizes silicon but not tungsten metal in the SiO2/Si/WN/W metal gate stacks of silicon wafers during advanced integrated circuit (IC) manufacture.Successfully led the research and development of new concepts, prototypes and processes of the first industrial single-wafer, hot-wall furnace based SELOX rapid thermal processing (RTP) tool. Investigated gate oxide integrity using SPV and corona oxide characterization of semiconductor (COCOS) methods.(see http://www.electrochem.org/dl/ma/203/pdfs/0884.pdf)Ultra-wide ribbon ion beam source R&D for high-current and ultra-low-energy ion implantors (6 months). -
Staff ScientistSyagen Technologies 1998 - 2000Mass Spectrometry Expert: Ion Trap, Reflectron Time-of-Flight (TOF), Atmospheric Pressure Photo-Ionization (APPI), Electro-Spray Ionization (ESI).High-Speed Ultra-Sensitive Chemical Reagent/Explosive/Drug Detection. Co-inventor of atmospheric pressure photo-ionizer (APPI) currently offered as an option by major mass spectrometer companies.
Yong Liu, Ph.D Skills
Yong Liu, Ph.D Education Details
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University Of SouthamptonPhysical Chemistry -
Uc San DiegoAtom-Resolved Molecule-Surface Dynamics (Si And Gaas) With Stm And Molecular Beams
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University Of BirminghamElectron-Molecule And Ion-Molecule Reactions
Frequently Asked Questions about Yong Liu, Ph.D
What company does Yong Liu, Ph.D work for?
Yong Liu, Ph.D works for Intel Corporation
What is Yong Liu, Ph.D's role at the current company?
Yong Liu, Ph.D's current role is Semiconductor process, integration, device engineering of Si CMOS, NVM; Ge/III-V photonics. A chemical physics, laser spectroscopy, & silicon atom-resolving surface scientist engaged in semiconductor nano technology..
What is Yong Liu, Ph.D's email address?
Yong Liu, Ph.D's email address is dr****@****hoo.com
What schools did Yong Liu, Ph.D attend?
Yong Liu, Ph.D attended University Of Southampton, Uc San Diego, University Of Birmingham.
What skills is Yong Liu, Ph.D known for?
Yong Liu, Ph.D has skills like Semiconductors, Characterization, Silicon, Ic, Semiconductor Process, Cmos, Cvd, R&d, Physics, Metrology, Design Of Experiments, Pvd.
Who are Yong Liu, Ph.D's colleagues?
Yong Liu, Ph.D's colleagues are Satish Talasu, Brian Kluge, Anna Kambhatla, Ahn Youngsoo, Daniel Braverman, Ben Brandt, Yong Teh.
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