Zia Khan

Zia Khan Email and Phone Number

Manager, Machine Learning @ Synopsys Inc
Sacramento, CA, US
Zia Khan's Location
Greater Sacramento, United States
Zia Khan's Contact Details

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About Zia Khan

Senior technical leader with experience in high-performance CPU, chipset, and graphics designs and EDA. Management expertise in managing design and EDA teams in driving solutions, formulating operation plans, and delivering results. Program management expertise in supporting foundry customers, planning, and executing projects, customer communications, and coordinating activities of internal and external teams.Authored 30+ technical papers, 6 patents, and gave keynotes at various conferences.

Zia Khan's Current Company Details
Synopsys Inc

Synopsys Inc

View
Manager, Machine Learning
Sacramento, CA, US
Website:
intel.com
Employees:
133841
Zia Khan Work Experience Details
  • Synopsys Inc
    Manager, Machine Learning
    Synopsys Inc
    Sacramento, Ca, Us
  • Intel Corporation
    Principal Engineer
    Intel Corporation Aug 2023 - Present
    Folsom, California, United States
    Enablement of internal and external customers for next-generation (18A & 14A) libraries. Responsible for analyzing libraries for PPA improvements. Defined new cell families for high-performance applications. Created library specifications to match industry standards and ease customer adoption.
  • Intel Corporation
    Principal Engineer
    Intel Corporation Nov 2021 - Aug 2023
    Folsom, California, United States
    • Led the design flow and methodology for next-generation Xeon processor design including physical implementation, formal verification and regression testing. Spearheaded DTCO effort to analyze standard cell usage and identified new cell families for library expansion. Chaired EDA vendor collaboration meetings to drive strategic initiatives including ML-based solutions for design implementation.
  • Synopsys Inc
    Principal Engineer, Library Analysis, Design Group
    Synopsys Inc 2013 - Dec 2021
    California, United States
    Created and grew a new group focusing on design technology co-optimization (DTCO) for improving standard cell libraries for PPA benefits, optimal synthesis, and P&R performance. Constructed analytical tools to help assess performance, power, and congestion issues in standard cell libraries. Drove development of library analysis features in Fusion Compiler which became a beneficial capability in improving libraries and tool performance.
  • Synopsys Inc
    Program Manager, Foundry Support, Implementation Group
    Synopsys Inc 2011 - 2013
    California, United States
    Program managed a key foundry customer on 28-, 20- and 16nm technology to enable technology node as first choice product for customers and to increase sales and usage.
  • Synopsys Inc
    Manager, Corporate Applications Engineering, Implementation Group
    Synopsys Inc 2008 - 2011
    California, United States
    Supervised dispersed corporate application engineering team supporting industry leading synthesis EDA tools across 5 international locations. Provided global support to Design Compiler users. Delivered 2 major software releases on schedule with high quality.
  • Intel Corporation
    Principal Engineer, Technical Program Manager, Design & Technology Solutions
    Intel Corporation 2005 - 2008
    • Led back-end team supporting multiple CPU design teams using 45- and 32-nm processes, enabling tapeout of leading CPU projects.• Developed design methodology for graphics and CPU designs, managed interfaces, and met tight deadlines.• Analyzed vendors, utilized ESL for future designs, and streamlined CAD tools, saving millions in CAD dollars.
  • Intel Corporation
    Senior Staff Engineer, Principal Engineer, Folsom Design Center
    Intel Corporation 1999 - 2005
    • Spearheaded the design team for the world's first 45nm microprocessor, Penryn, implementing new flow and synthesis tools.• Pioneered algorithms for improved buffering and low power implementation in high frequency CPU design.• Collaborated with team members to set the stage for innovative design solutions at Intel Corporation.
  • Intel Corporation
    Staff Engineer, Graphics Component Division
    Intel Corporation Jan 1997 - Jan 1999
    Led synthesis methodology team for a high volume graphics chip creating a flow for implementing mega blocks with complex control and datapath elements. This very successful chip and it derivatives sold more than 500 million units. Variants of flow are widely used across company.Developed area (15%) and power optimization (25%) flows for large ASIC designs which are now extensively used in ASIC and SoC designs. Worked with EDA vendor to enable more efficient clock gating for low power.
  • Intel Corporation
    Staff Engineer, Da Manager, Pci & Graphics Component Divisions
    Intel Corporation 1989 - 1997
    Led synthesis methodology team for a high-volume graphics chip devising a flow for implementing mega blocks with complex control and datapath elements. Derivatives of this chip sold more than 500 million units. Variants of flow are still widely leveraged across company.Developed Intel's first ASIC development flow to enable Intel's entry in ASIC business with ability to target multiple fabs using COT model to opportunistically utilize multiple fabs as product demand varied.

Zia Khan Skills

System On A Chip Algorithms Debugging Integrated Circuits Logic Synthesis Rtl Design Microprocessors Dft Processors Intel Asic Timing Vlsi Verilog Integrated Circuit Design Rtl Coding Soc Eda Semiconductors Physical Design Static Timing Analysis Low Power Design Application Specific Integrated Circuits Ic

Zia Khan Education Details

Frequently Asked Questions about Zia Khan

What company does Zia Khan work for?

Zia Khan works for Synopsys Inc

What is Zia Khan's role at the current company?

Zia Khan's current role is Manager, Machine Learning.

What is Zia Khan's email address?

Zia Khan's email address is zi****@****ail.com

What schools did Zia Khan attend?

Zia Khan attended Virginia Tech, University Of Kentucky.

What skills is Zia Khan known for?

Zia Khan has skills like System On A Chip, Algorithms, Debugging, Integrated Circuits, Logic Synthesis, Rtl Design, Microprocessors, Dft, Processors, Intel, Asic, Timing.

Who are Zia Khan's colleagues?

Zia Khan's colleagues are E.h.asanul Ajhar E.h.asanul Ajhar, Kirill Shutemov, Sebastian Cordoba, Widad Nasir, Thomas Phillips, Irene Tan, Paul Cordeiro.

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    gmail.com, mashreqbank.com
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