I am highly motivated and passionate about FPGA development and verification. I constantly develop my competencies and master new ones that may be needed at my work. I by myself and at a proficient level mastered verification and learned UVM. I can and successfully work both independently and in a team. I have a positive mindset and looking for ways to achieve results. I am not afraid to take on responsibility and additional responsibilities.Projects experience:Development of verification environments for DSP and communication systems using UVM (with RAL). I am responsible for the test plan, test cases and environment. Wide use of AXI4(LITE) and AXI4STREAM buses, DDR4 models, ethernet, SPI protocols. Lead engineer experience.Use constrained random stimulus (CRT) and coverages for test automation and the test plan control. Use a basic subset of SVA. Development of RTL for the DSP and communication submodules with high-speed buses (mostly ethernet). Lead engineer experience.Hard skills:- Knowledge of DSP principals with experience in development verification models.- Knowledge of verification principles and strategies with experience in many different projects.- Knowledge of FPGA architecture and RTL coding styles and methods.Skills and competencies:- development of complex testbenches using UVM (with DPI-C, basic SVA, RAL, layered protocols, and out-of-order agents), development of automated constrained random test cases with coverage and error collection;- development of complex testbenches in VHDL with using OSVVM (multilanguage testbenches, basic PSL);- working closely with a team of algorithmic mathematicians to develop reference models;- development of verification agents for custom protocols (layered, out-of-order);- development, simulation of behavior, and hardware implementation of algorithms based on FPGA. Experience with Xilinx Spartan 6/7, Kintex 7/us, Intel Cyclone 2/3 FPGA families with using transceivers, Ethernet 1G, DDR4, custom interfaces);- In deep knowledge of VHDL (including VHDL-2008), In deep knowledge of SystemVerilog(including DPI, base SVA, constraints and coverage), base in C/C++, Matlab, TCL and base Python, - CADs: Vivado, Modelsim, Questa, base experience with ALint-pro, Matlab.- knowledge of the architecture of modern FPGAs. Ability to implement own cores;- development of projects with a complex clock hierarchy;- optimization of time delays inside the crystal