• 7+ years of Experience in Physical Design industry.• Experience in handling High utilized and critical blocks with PLL.• Responsible for Netlist to GDS delivery of partitions.• Owned power-gated design with rectilinear and multiple power domains.• Static timing analysis (STA), fixing DRV’s• FEV, VCLP, Physical Verification, Timing Caliber, Crosstalk delay, xor2spec• Signal EM, IR/RV, Hot-nets, Hot-spots• Familiar with cheetah-2 and RDT, placement and routing flow, RTLFP (Full-chip layout)