* Owns overall CPU design execution from concept to tape out across a 190+ world wide team including logic, verification, and physical design disciplines. Leads the overall core leadership team. Create and drive budget and schedule commitments to deliver program goals.* SOC Chip Manager - drives program deliverables on Power processor p11 program

Responsible for managing program execution on Power Processor Core:• Overall core execution Program Manager, interlocking with external stakeholders on project deliverables. * Senior manager, managing the entire 85+ core engineering organization

Responsible for leading core verification execution on Power Processor.

Manager and technical lead verifying Infinity Fabric transport and cross-die functional components, used in AMD's servers, clients, graphics, and SCBU products offerings:• As technical manager, work closely with RTL designers and verification teams to define verification strategy, architect testbench environment, and functionally verify the design. • Communicate with stakeholders and SOC teams on feature delivery, strategies, status, schedules, and project metrics. Drive meetings as needed to define goals and vet potential issues/blocks.

Manager and technical lead verifying Infinity Fabric transport and cross-die functional components, used in AMD's servers, clients, graphics, and SCBU products offerings:• As technical manager, work closely with RTL designers and verification teams to define verification strategy, architect testbench environment, and functionally verify the design. • Communicate with stakeholders and SOC teams on feature delivery, strategies, status, schedules, and project metrics. Drive meetings as needed to define goals and vet potential issues/blocks.

Responsible for integrating IPs into server-SoC:• Lead server SoC verification team to integrate IPs (x86 core, north ridge, and IO subsystem) into AMD’s server-SoC.. Integration includes first time functional bring-up of the entire SoC.• Coordinated IP deliverables to SoC and communicated dependencies and issues as needed, driving weekly IP/SoC sync meetings and releasing code to physical design team, emulation, and regression teams.