Adam Hartman Email & Phone Number

Mountain View, Ca, Us

Santa Clara, Ca

- Designed and implemented a wide-ranging improvement to a proprietary, real time logic verification and validation flow which added numerous features while decreasing synthesis runtime by 5%- Designed and implemented a timing-aware logic restructuring and partitioning flow which increased the speed of resulting logic by 3% while decreasing synthesis runtime by up to 30%- Designed and performed proof-of-concept experiments for synthesizing computation specified in a high-level language to DSP/arithmetic hardware- Provided deadline-critical development and debugging of synthesis software for internal RTL developers

Mountain View, Ca

- Designed and implemented a method for significantly enhancing timing debug information of RTL designs implemented on large hardware emulators- Designed and implemented an efficient process for creating timing graphs for extremely large RTL designs- Designed and performed experiments to understand the capabilities of an incremental RTL synthesis/placement/routing flow and used the results to provide project planning guidance to management

Pittsburgh, Pa

Designed, implemented, and published numerous experiments related to design exploration for embedded systems with the purpose of improving system lifetime

Redmond, Wa

- Developed a scriptable, driver-based test framework for the Plug and Play subsystem which simplified test development and increased the productivity of other test engineers- Updated and maintained test suites for various Windows APIs

Ms/Phd, Computer Engineering, 3.96/4.0

Bachelor Of Science (Bs), Electrical And Computer Engineering, Computer Science, 3.44/4.0