Ashwin S. Email & Phone Number

California, United States

Redmond, Washington, Us

Joined Microsoft via its acquisition of Fungible. Vision is to use Data Processing Unit (DPU) technology to improve the efficiency, reliability, performance and economics of Azure data-centers.

Involved in the architecture and development of various components of Fungible's software from the novel DPU optimized operating system to control plane based micro-services.- Prior to the acquisition, Fungible developed a high-performance scale-out storage solution called Fungible Storage Cluster (FSC) using a DPU enabled storage appliance equipped with commodity SSDs.- Worked on a framework for high-level applications (ApacheSpark, SQL engines) to offload IO intensive portions of workloads onto the DPU appliance with minimal changes to business logic to improve performance and efficiency.- Tuned the solution to achieve up-to 4x speedup on certain queries in the TPC-H benchmark suite on cold data.- Developed several components (events, alerting, data categorization and processing) for a high throughput Telemetry system.- Worked on a Software-Development-Kit (SDK) that exposes APIs at various abstractions to enable customers to fully utilize the programmability of DPU hardware.- Analyzed and tuned the novel Fungible True-Fabric congestion control protocol for large data-center network deployments.

Cupertino, California, Us

Performance Architect for multimedia IP subsystems - Camera, Display, Video/Image Accelerators - for Apple A10 through A14 SoCs.- Analyzed and optimized media hardware accelerator memory access patterns and usage of system caches.- Collaborated with Silicon, Platform and Software teams to simulate top customer use cases and investigate data flows between CPUs, GPUs, Camera/Video, ML, and I/O components to identify performance issues early in the SoC project. This saved Apple months of engineering cost and time.- Architected a dynamic HW based buffer sharing scheme for Image Signal Processor (ISP) media pipelines that resulted in a 50% reduction to overall buffer area while maintaining the same performance. Apple has applied for a patent for this work.- Analyzed and tuned network-on-chip QoS schemes to deliver optimal network sharing and achieve real-time performance goals.- Worked with firmware and driver teams to optimally program HW accelerators to hit performance goals for key product use cases.- Scripted and automated large simulation workflows to achieve quick turnaround times on critical HW design decision experiments.- Worked with ASIC RTL and DV teams on performance test plans that caught design bugs early in the project saving the organization many engineering hours.

Santa Clara, Ca, Us

Design implementation methodology and EDA/CAD tooling.

Sunnyvale, California, Us

SRAM Memory Compilers and Phase Locked Loop (PLL) Design.

Master’S Degree, Electrical And Computer Engineering

Bachelor'S Degree, Electrical And Electronics Engineering

High School