Ashwin S.

Ashwin S. Email and Phone Number

Principal Software Engineer @ Microsoft
California, United States
Ashwin S.'s Location
San Jose, California, United States, United States
Ashwin S.'s Contact Details

Ashwin S. personal email

n/a
About Ashwin S.

Experienced engineering leader with a track record of delivering complex projects on time with high quality.Domain expertise with DPU and datacenter infrastructure technologies, with a deep understanding of SoC/HW architectures and the SW stacks that run on them.I enjoy tackling tough problems that involve large amounts of data, strict performance requirements and HW-SW co-design.

Ashwin S.'s Current Company Details
Microsoft

Microsoft

View
Principal Software Engineer
California, United States
Website:
microsoft.com
Employees:
231118
Company phone:
0124 415 8000
Ashwin S. Work Experience Details
  • Microsoft
    Principal Software Engineer
    Microsoft
    California, United States
  • Microsoft
    Principal Engineering Manager
    Microsoft Jan 2023 - Present
    Redmond, Washington, Us
    Joined Microsoft via its acquisition of Fungible. Vision is to use Data Processing Unit (DPU) technology to improve the efficiency, reliability, performance and economics of Azure data-centers.
  • Fungible, Inc.
    Principal Engineer
    Fungible, Inc. Dec 2019 - Dec 2022
    Involved in the architecture and development of various components of Fungible's software from the novel DPU optimized operating system to control plane based micro-services.- Prior to the acquisition, Fungible developed a high-performance scale-out storage solution called Fungible Storage Cluster (FSC) using a DPU enabled storage appliance equipped with commodity SSDs.- Worked on a framework for high-level applications (ApacheSpark, SQL engines) to offload IO intensive portions of workloads onto the DPU appliance with minimal changes to business logic to improve performance and efficiency.- Tuned the solution to achieve up-to 4x speedup on certain queries in the TPC-H benchmark suite on cold data.- Developed several components (events, alerting, data categorization and processing) for a high throughput Telemetry system.- Worked on a Software-Development-Kit (SDK) that exposes APIs at various abstractions to enable customers to fully utilize the programmability of DPU hardware.- Analyzed and tuned the novel Fungible True-Fabric congestion control protocol for large data-center network deployments.
  • Apple
    Performance Architect
    Apple Jan 2016 - Dec 2019
    Cupertino, California, Us
    Performance Architect for multimedia IP subsystems - Camera, Display, Video/Image Accelerators - for Apple A10 through A14 SoCs.- Analyzed and optimized media hardware accelerator memory access patterns and usage of system caches.- Collaborated with Silicon, Platform and Software teams to simulate top customer use cases and investigate data flows between CPUs, GPUs, Camera/Video, ML, and I/O components to identify performance issues early in the SoC project. This saved Apple months of engineering cost and time.- Architected a dynamic HW based buffer sharing scheme for Image Signal Processor (ISP) media pipelines that resulted in a 50% reduction to overall buffer area while maintaining the same performance. Apple has applied for a patent for this work.- Analyzed and tuned network-on-chip QoS schemes to deliver optimal network sharing and achieve real-time performance goals.- Worked with firmware and driver teams to optimally program HW accelerators to hit performance goals for key product use cases.- Scripted and automated large simulation workflows to achieve quick turnaround times on critical HW design decision experiments.- Worked with ASIC RTL and DV teams on performance test plans that caught design bugs early in the project saving the organization many engineering hours.
  • Nvidia
    Intern
    Nvidia May 2015 - Aug 2015
    Santa Clara, Ca, Us
    Design implementation methodology and EDA/CAD tooling.
  • Synopsys
    Research And Development Engineer
    Synopsys Jan 2014 - Jul 2014
    Sunnyvale, California, Us
    SRAM Memory Compilers and Phase Locked Loop (PLL) Design.

Ashwin S. Skills

C C++ Verilog Matlab Algorithms Vlsi Computer Architecture Cadence Virtuoso Eda Asic Perl Unix Linux Spice X86 Assembly Tcl Application Specific Integrated Circuits Very Large Scale Integration Calibre

Ashwin S. Education Details

  • Georgia Institute Of Technology
    Georgia Institute Of Technology
    Electrical And Computer Engineering
  • Birla Institute Of Technology And Science, Pilani
    Birla Institute Of Technology And Science, Pilani
    Electrical And Electronics Engineering
  • Delhi Private School, Sharjah
    Delhi Private School, Sharjah
    High School

Frequently Asked Questions about Ashwin S.

What company does Ashwin S. work for?

Ashwin S. works for Microsoft

What is Ashwin S.'s role at the current company?

Ashwin S.'s current role is Principal Software Engineer.

What is Ashwin S.'s email address?

Ashwin S.'s email address is as****@****ble.com

What schools did Ashwin S. attend?

Ashwin S. attended Georgia Institute Of Technology, Birla Institute Of Technology And Science, Pilani, Delhi Private School, Sharjah.

What are some of Ashwin S.'s interests?

Ashwin S. has interest in Mathematics, Physics, Computer Architecture, Sports, Books, Stock Market, Food, Health, Education, Environment.

What skills is Ashwin S. known for?

Ashwin S. has skills like C, C++, Verilog, Matlab, Algorithms, Vlsi, Computer Architecture, Cadence Virtuoso, Eda, Asic, Perl, Unix.

Who are Ashwin S.'s colleagues?

Ashwin S.'s colleagues are Valle Srieeshae, Minye Sat, Anusha Kn, Merve Dincer, Saurabh Sharma, Rajan Khehra, Gladys Del Carmen Pichardo.

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