Chun-Sup Kim Email & Phone Number

San Jose, Ca, Us

San Jose, Ca, Us

Lowell, Ma, Us

Clock and Analog Front End(AFE) design for High Speed Serial Link Applications - Working on design of high speed adc clock generation for 56Gbps DSP based PAM4 SerDes, and TI SAR adc evaluation for 65GS/s coherent receiver [16nm Finfet CMOS].

San Diego, Ca, Us

- Developed design concept of advanced wireless communication RF IC, including 6G full band (up to 7.125GHz) 802.11ax WLAN applications [14nm Finfet CMOS] for leading transmitter module.- Designed and developed RF ICs, such as RF 5G Drive Amplifier, TIA / Baseband analog filter amplifier for WLAN 802.11ax applications [28nm/14nm CMOS].- Evaluated RF TX Power Control / Calibration and prepared design documents and test plans for WLAN 802.11ax applications [28nm CMOS].- Completed Central-Office Transmitter design for G.fast AFE such as Delta-sigma DAC (12bit, Low OSR, Sampling frequency of 848MHz) and TIA (Trans impedance amplifier) plus Smoothing filter (Rauch, 3rd order) with process calibration [65nm CMOS].

Fremont, Ca, Us

- Worked/evaluated on CPE Transmitter design for G.fast AFE including Delta-sigma DAC/TIA/Smoothing filter(Rauch) with process calibration [65nm CMOS] - Designed high performance Line driver IC [SiGe BiCMOS] for high speed up to 106MHz and low power dissipation with integrated boost dc-dc converter using charge-pump power generation(14.5V and -2.5V) in G.fast/xDSL modem applications up to 14.5dBm(CPE)/19.5dBm(CO), Class-G Capability

San Jose, Ca, Us

- Developed the CML Line driver, Emphasis and Serializer for 1.5Gbps and 3.0Gbps Serial ATA PHY- Developed low Jitter PLL(565MHz) and DCXO(35MHz) for ADSL and VDSL- Designed high speed Sub flash ADC for High speed pipeline ADC(12bit, 35/70MSPS) for VDSL - Designed PGA plus Line Driver on Analog Front End IC for ADSL/ADSL2+ CPE applications- Published 700mW High speed Line Driver for ADSL Central Office(Published on ISSCC2003, JSSC Dec, 2003) – Class-H