Kai C. Email & Phone Number

Santa Clara, California, US

• Led a group of engineers to do both IP DFT integration and validation including Array BIST, Structural Test Fabric, Scan, Debug Test Fabric, iJTAG network and HVM usage models.
• Delivered DFT collaterals to server SOC team and work with SOC on bug fixes.
• Established overall clock domain crossing (CDC) methodology for the server products with both QuestaCDC and Spyglass CDC.
• Delivered IP Spyglass DFT (SGDFT) with scan insertion 99% and ATPG coverage above 95%.
• Chaired DFT integration and validation reviews before tape-in.

Santa Clara, California, US

• Implemented project level clocking architecture in RTL including modeling PLL, clock distribution, clock compensation; responsible for enabling clock power-up sequences in high volume manufacturing and various.
• Designed clock related DFT features used in post-silicon such as ODCS (On-Die Clock Shrink), LCP (locate critical path) and fuse download mechanism; Collaborated with product engineer team to define and analyze.
• Conducted the clock skew measurement to correlate with timing model; resolved several critical power-on sightings related to clock alignment and determinism.

Santa Clara, California, US

• Led and mentored three junior engineers in defining u-architecture for several DFT/DFM/DFD features and controllers including Scan, TAP, clocking modulation for at-speed debug, u-breakpoint controller, IDVP and others.
• Defined project SCAN insertion criteria and provided guidance in STA methodology and back annotation flow; enabled compression mode in SCAN implementation and ATPG patterns to achieve 4X better performance in test time.
• Mentored several junior engineers in both failure analysis and component debug group in utilizing different ATE and optical probing platforms to root-cause several critical electrical bugs found during silicon.
• Led the efforts in design with component and system debug tool groups to deliver the user functions and interface for major DFT/DFD features, which were used by various debug groups; delivered the required collaterals.
• Delivered signature enabled functional tests generated by LBIST alike mechanism to increase at-speed test coverage by 5% required to satisfy product shipment criteria.
• Designed MCI (Multiple Core Interface) and JTAG u-architecture to enhance parallel core testing and scaling to reduce test time and tester memory.

o Owned standard datapath custom blocks and synthesized blocks in Itanium server product, worked on schematics and layout, completed full chip timing analysis, timing convergence and constraints as well as analyzed noise glitch, electrical rule violations, and reliability verification. o Worked on LLC data/tag array floor planning, and spice simulation.