Clive Walker Email & Phone Number

Over 10 years experience in successfully leading the planning, design and implementation of highly complex SOC’s using the latest design tools and techniques.Security implementation.Expert in SoC security architecture implementation and review especially for sigital video SoCs.Project Management• Extensive experience managing design, integration and delivery of a devices with focus on resource planning, critical path analysis, project tracking, project trade-offs and risk mitigation.ASIC Design• Expert knowledge of modern design ASIC and FPGA tool experience with Design compiler & Synplify, Primetime and floorplanning with IC Compiler.• Wide experience of implementing full design flows from RTL to GDS, including low power design techniques• Expert with RTL Design languages: Verilog & SystemVerilog, some VHDL.• Experienced verification user of VCS, NCSim and Questa with some UVM experience.• Over 10 years` experience with ARM processors, TrustZone and AXI, AHB, APB bus matrices and peripheral design.• Expert in ASIC security architecture and implementation.Languages• Working French: Diplôme de Langue issued by the Alliance Française, 1999.• Mother tongue English.Achievements• Front end integration team leader and sub-project manager for the successful implementation of Marvell’s 1901 Powerline Baseband SOC.• Project manager for Broadcom`s VideoCore III BCM2707 multimedia co-processor chip. Team included 70 engineers. Hardware design team leader for industry leading Image Sensor Pipeline.• Lead Engineer responsible for defining and successfully delivering multimedia IP for a low cost 3G baseband device for a multi-site international team.

Listed skills include Hardware Architecture, System On A Chip, Floorplanning, Very Large Scale Integration, and 27 others.

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  Imperial College London

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