Sr. IC Design Engineer and Co-founder – Microdisplay IC Design Mgr/Lead : • Sr Designer on Syndiant’s initial product, a 1080p LCOS Microdisplay IC - 0.25um • Performed circuit design of custom SRAM, high voltage pixel memory, and power grid.• Worked with CTO to translate core IP into display algorithm and hardware. • Designed and implemented color calibration gamma correction algorithms.• Performed Verilog design of FPGA video data-path for triple clock domain data convolution (incoming-DRAM-Display). • Lead IC Designer, and Project Lead on all 6 subsequent field-sequential and color-filter LCOS Microdisplay ICs • • Designed improved 250MHz 0.18um SRAM memory for reduced power and modularity.• Designed high voltage SRAM display memory, and performed power grid analysis.• Integrated SPICE and SDF simulation results in custom mixed-signal design flow.• Identified fundamental solution for next generation system to fast-scan architecture.• Architected next generation microdisplay to meet advanced system requirements.• Coordinated IC design team with architecture requirements and ASIC design team.• Coded behavioral Verilog for microdisplay main controller, datapath, and test vector generation.• Implemented and debugged all digital control and datapath logic.• Led process transition from 0.18um to 0.13um process.• Architected and designed IC power down, redundancy, and test-mode systems.• Project leader and resource manager of IC designs.• Estimated scope, resources, and budget for IC design projects.• Defined tool requirements for successful tape-out during mid-project tool change• Supervised local and off-shore, physical design and synthesis/place-and-route personnel. • Current patent applications: 20120154370, 20110150501

IC Design/Mask Engineer:• Flash, BIST chip: • Developed voltage stepper for various Flash test states. • Designed test circuit to read and log depleted bits/columns for Flash memory module. • Built correlation logic for all test modes to mode register, counters, SRAM, and external• Performed final layout of numerous chip modules.• Performed digital logic verification test of chip Project for Covalar Inc).• Redesigned differential input drivers for selectable 2.5V DDRI and 1.8V DDRII 500MHz I/O drivers. • Sense-amp design for Dual-Port DRAM cells. • Performed layout, and chip verification of a, 256Mb DRAM, test chip design.• Patents: 6,310,880 6,256,221 6,222,786