David Dunn Email & Phone Number

Sammamish, Wa, Us

Seattle, Washington, United States

Bellevue, Washington

Principal Engineer on vSphere.Responsible for architecting security and CPU features in VMware’s ESX hypervisor.Led VMware’s response to the Spectre, Meltdown, and L1TF sidechannel vulnerabilities.Champion and architect for security features such as vTPM, SGX support, SEV-ES support, andrunning Windows Credential Guard nested under ESX.Lead team working to support realtime workloads under ESX, moving guaranteed response timein VMs from the multi-millisecond to below 20us.Anchored a new VMM team in Bellevue, mentoring new hires as we built the team from twoengineers up to ten engineers of all levels.Mentored several mid level engineers to help them expand scope and impact.

Greater Seattle Area

Developed large portions of the early product software, test infrastructure, and automated tests.Responsible for platform engineering, including specification of semi-custom server platform.Mentored new engineers as Qumulo grew from around 10 employees to over 50.Active in planning, engineering process, coding, and bug triage activities.

Greater Seattle Area

Managed team responsible for VCMP. VCMP is a BigIP feature that runs multiple copies of BigIP software inside virtual machines within a single F5 chassis.Led the effort to bring the Corensic engineers up to speed on F5 software and processes.Drove bug fixes, automated testing, and minor feature improvements for VCMP.Helped increase the stability and ship readiness of VCMP in a short release window.

Managed the Development and QA efforts for Corensic's Jinx product.Provided technical support behind the marketing and sale of Jinx. Including demos, documentation, customer support, and sales engineer roles.Rewrote significant portions of the hypervisor to add support for linux guests and 32bit windows.Played a significant role in transferring Corensic's intellectual property and engineering team into F5.

Architected the dynamic translator software used in Nvidia's Denver CPU.Trained a team of 20 software engineers on dynamic translation and CPU architecture.Liason between the microcode/software team and the CPU logic design team.Key contributor in updating Nvidia's GPU kernel drivers for Windows-7.Technical liason between Nvidia and Microsoft, helped define windows-7 WDDM extensions.Internal liason between the windows driver team and the Fermi hardware architecture team.

Architected the joint Microsoft / Transmeta solution for pay-for-use PC platform (FlexGo).Designed and documented x86 instruction set extensions to meet Microsoft's requirements.Led a joint engineering team of Transmeta and Microsoft engineers to implement the x86 extensions and incorporate use of those extensions into Microsoft's pay-for-use system.

Added floating point support to Microsoft's Phoenix research compiler.Code the .NET object model support in the Phoenix backend optimizer.

Architected the floating point and DMA support for Transmeta's Efficeon processor.Coded reference emulator for x86 floating point instructions: x87, MMX, and SSE.Defined software invariants to provide deadlock-free DMA with sequential consistencyRewrote the floating point microcode for Crusoe to fix compatibility with x87 and increase performance.Tuned Crusoe CMS to improve responsiveness.

Led dynamic translation team (JIT) that allowed PA-RISC programs to run on ia64 architecture.Designed translator engine and signal handling modules.Enhanced HP's PA-RISC compiler backend to properly schedule for the PA-8000 chip.Added 64bit support to the HP compiler.Tuned the optimizer for increased Fortran performance on PA-RISC.