David Kaplan Email & Phone Number

Lower Gwynedd, Pennsylvania, United States

• Skilled in the use of Cadence design and simulation tools including: Virtuoso, Maestro, Viva, Xcellium, Simvision, LiberateAMS, and SI netlister
• Utilized Verilog and SystemVerilog to write RTL for various digital circuits including synchronous state machines, clock dividers/generators, and custom control logic
• Modified the design of an existing master-slave delay locked loop to improve overall performance
• Detailed and verified the pipelined clocking scheme of a 100MHz, 7-stage pipeline ADC
• Designed digital behavioral models of switched cap analog blocks, and wrote Verilog RTL for a complex digital calibration algorithm for the above pipeline ADC
• Utilized LiberateAMS to create liberty timing models of custom circuit designs including, levelshifters, differential switch drivers, and custom clock dividers

Lower Gwynedd, Pennsylvania, United States

• Created digital and mixed-signal test benches using Verilog/VerilogAMS to drive the characterization and verification of custom circuit blocks
• Executed digital functional simulations using Xcellium to verify the performance of digital designs
• Created digital real number behavioral models of custom analog blocks for use in digital functional simulations to save simulation time and resources
• Utilized Cadence SI netlister utility to generate customized Verilog and CDL netlists of circuit blocks

Lower Gwynedd, Pennsylvania, United States

• Worked closely with engineering and layout team members to design and characterize various analog, mixed-signal, and custom digital circuit blocks for implementation in ASIC projects
• Wrote various scripts to assist with day-to-day tasks, including heavy use of RegEx matching in Perl
• Ran circuit simulations to put together detailed characterization reports

• Researched anonymous routing techniques and network traffic patterns in order to verify analytical results
• Used NS3 network simulator to design and test anonymous network topologies and simulate more practical traffic models
• Co-authored conference paper submitted to IEEE International Conference on Communications

East Fishkill, NY

• Used Cadence SKILL language to develop time-saving automation programs
• Worked in conjunction with design engineers to complete 6 programming projects

Master'S Degree, Electrical Engineering

• Designed and built a “Smart Cat Feeder” machine vision system using a Raspberry Pi and camera to visually detect two different cats and.

Bachelor'S Degree, Electrical And Electronics Engineering, 3.64

Activities and Societies: Tau Beta Pi, Delta Chi, Lehigh Marching 97, Lehigh Wind Ensemble, Rossin Junior Fellow, IEEE