A quick learner, VLSI enthusiast and an engineer, currently working for Samsung Semiconductor (SSIR) Foundry.My focus lies in Synthesis, Floor-planning, Power-planning, Placement, CTS, Routing and Static Timing Analysis (STA) at the block level.I actively engage in analyzing and addressing sign-off checklists, with a keen eye on Physical verification aspects such as DRCs and LVS.Capable of utilizing TCL and Unix commands for effective scripting, enhancing efficiency and accuracy in semiconductor workflows.Eager to explore new horizons of semiconductorengineering and continually enhancing my skills. Open to network, collaborate and to learn from seasoned professionals who share the same passion for innovation and excellence.Let's connect and explore the possibilities together!!