Mike Duggan Email & Phone Number

Redmond

Redmond, Washington

Greater Atlanta Area

• Developed semi-auto reporting and tracking Infrastructure database for Motorola's Failure Analysis Lab (FAL)• Diagnose fielded failures to root cause and issue corrective actions to organizational units (Supply Chain, Manufacturing, Hardware, Software, Mechanical and Repair Engineering)• Coordinate Vendor specific component analysis when required.• Unique training with X-ray, Endoscope, Spectrometer, Flir and BGA placement/removal station.

• Lead Engineer Overseas ODM Development of PMP (Portable Media Player). Responsible for hardware capabilities assessment of ODM engineering facility in Korea. Conducted on-site facility qualification and RFQ discussions as HW liaison. Responsible for ESM facility assessment in mainland China,• Lead Engineer for DCH6416 OCAP Cable-Card ASTB. Developed Product Hardware Roadmap documents. Coordinated team of 12 engineers, providing comprehensive Test Plans, resource assignment and design verification analysis. Conducted Phase Reviews, Schematic and Layout reviews, and weekly progress analysis meetings. Analyzed, formatted and presented BU management with Phase step through reports and risk analysis/mitigation assessments.

Greater Atlanta Area

• Continued my role as Audio DSP Assembly Develper for the Digital Media Systems group.• Conceived, designed and developed a DC to 3GHz switch with 80dB Isolation and 0.5dB ins. loss at 1GHz – Stackable with remote activation & monitoring and on-board self actuating, configurable plug-in sensor modules

• Developed DSP Assembly code for AC3 encoder with 5.1 Pass thru support for three different development teams simultaneously. Reviewed and modified each hardware design to be compatible with a single compiled downloadable. Coordinated development testing with Dolby Labs and received Dolby certification for each teams design. Completed same for MPEG L2, and AAC LC for local team. MOT 56303 DSP platform• Engineering Core Team Leader for FPGA to ASIC conversion of BTSC Stereo encoder. Conducted and managed third party negotiations, cost control, project timeline and engineering design details. Received training in both Verilog and VHDL for FPGA modifications as well as simulation toolset.• Primary Design Engineer & Core Team Leader for RF signal Manager Passive combiner modules. Developed, implemented and conducted DVT planning, Designed product and test methodology to achieve Cpk values of >2 • Designed microprocessor interface and communications board for UC-4. Conceived and captured the schematic, layed out the design using Veribest, and coded the embedded firmware in assembler on a Hitachi 3144 processor.

Atlanta

• Designed the 9815 Extended Interface module (EIM) employed in the 9825 Modulator chassis. Determined interconnection requirements and established EPS guidelines for Plug & Play hardware, as well as interconnection layout. Implemented unique faceted rear plate design, receiving two patents. Module loads 19 “F” connectors and 24 data contacts in 1.875” by 5RU and maintains reasonable cable routing.• Developed stripline interfacing for EIM and created Trojan Horse right angle coax connector for D-subminiature Housing with third party vendor FCT allowing almost total eradication of cabled interconnections inside the EIM.

• Developed ATE for 9800 Series BTSC Stereo Encoder• Proposed and led development of the 6385 BTSC Stereo Encoder employing the 9800 series Vertical mount PCB's in a flat mount 1 RU package.