Eric Snow Email & Phone Number

Santa Clara, California, United States

Santa Clara, California, United States

Strategic leader & principal design engineer for Intel’s global photonics wafer sort capability. Responsible for sort technology development and deployment, focused on delivering cutting-edge capabilities to meet the required capacity while minimizing cost of test, including selecting hardware vendors, building out a bill of materials, and transferring the test process to the factory site. Partnered with divison product and R&D teams, as well as factory integration and test teams, to predict and deliver test technology to meet the complex needs of a dynamic component roadmap. Managed team of 8 engineers and 1 technician to success in delivering multiple generations of products to market. • Conceptualized and drove adoption of high-parallelism photonic test tools, including multi-channel single-die and multi-channel multi-die capabilities.• Successfully scaled and ramped over $25m in capital expenditures to enable production test at factory.• Wrote & developed internal software tools for data visualization, analysis, databases, and layout optimization.• Drove conversion of test software to .NET platform supporting full factory integration with SEMI-standard compliance.• Integrated mixed-signal instrumentation including SMUs, ESA, OSAs, power meters, switches, and attenuators into a standard-form factor ATE test tool.

Santa Clara, Ca

Principle Engineer & Group Leader responsible for developing new photonic sort manufacturing technologies and R&D test capabilities. Own development roadmap for testing new products from prototype through production and ensuring tools meet capacity and capability commitments.

Hillsboro, Or

Managed test file generation for new product introductions, drove management of software tools used by internal and external groups and developed processes to ensure high tester uptime and data quality. Routinely collaborated with groups including components research, device, process integration, automation, advanced design and quality and reliability.• Designed and developed test software infrastructure and programs for a large capital investment in new parametric test equipment. Defined tool requirements (features, accuracy) and analyzed tester’s ability to meet requirements. Worked closely with vendor engineers to design API and data exchange formats. Performed data matching analyses to demonstrate tool capability and bring systems into production.• Improved cycle time for both development and commercial products by planning and designing test structure layout and row placement to optimize test time.• Managed software tool enhancement project, which involved working cross-functionally to improve workflow and improve test process consistency. Number of quality events was reduced to near 0 as a direct result of the project.• Managed 6 (3 TD, 3 product) test NPIs with extremely high quality. Achieved through both close coordination with device/integration groups and attention to detail in preparing test specs and probing coordinates.• Awarded PTD Divisional Award for initiative to optimize hardware and algorithms for device group testing that reduced test time by factor of 10.• Awarded D1C Divisional Award for rapidly troubleshooting and resolving an algorithm fault that was incorrectly binning parts, costing significant engineering rework time and product loss.• Awarded Components Research Divisional Award for developing and deploying a new method to extract electron mobility using parametric testers.

Founded a consultancy that assisted small businesses in Santa Barbara with their IT needs.• Designed and implemented a network for a renovated office building. Installed and configured managed switches and Windows Server 2008 AD.• Installed wireless bridge to satellite office and established on-site and off-site backup solutions.• Developed and tested UPS solution for lab workstations and instruments.

• Advisor: Dr. Umesh K. Mishra• Thesis Title: “InGaAs and GaN Field-Effect Transistors via Direct Wafer Bonding”• Developed process and constructed novel III-V transistors by bonding InGaAs Source/Gate to GaN Drain.

Set up and maintained IT infrastructure.

Assisted with EUV lithography experiments at the Advanced Light Source at LBNL.

Worked on conditioning control software for RF cavities in Spallation Neutron Source.

Phd, Ece

Thesis topic: InGaAs-GaN Bonded Field-Effect Transistors

Masters, Ece

Bs, Eecs