Eric Stevens Email and Phone Number
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Eric Stevens personal email
Worked on FW and Process for MNAND UFS Products.Spent two years learning NAND working as a product engineer on new TLC NAND design. Managed (and performed) Design Validation Checkouts, New Reticle Integration (Validation and Management through FAB to TEST).Previously, Lead Engineer for PCIe Enterprise SSDs. Experienced in debugging FW and HW issues. Development of test flows and debug tools.8 years experience in ATE (Teradyne and Advantest), writing programs for ASIC, PowerPC, Mixed Singal Cell Phone Controllers, Hard Drive Controllers, and DRAM and PSRAM.Flexible and well rounded engineer. Have had the opportunity to work on large Software and Hardware projects. Comfortable with both a scope and building C++/Python/Perl Frameworks.Worked on large scale projects involving multiple international sites. Lived in Germany 1 year.
Advantest America, Inc.
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Systems Memory EngineerAdvantest America, Inc. Jun 2022 - PresentBoise, Idaho, United States
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Lead EngineerBoise State University Aug 2021 - PresentProvides security services to state, local and tribal organizations/infrastructures through the Institute for Pervasive Cybersecurity, an educational, experiential, and innovation hub for higher education institutions hosted at Boise State University. Additionally, provides mentorship and leadership to affiliated students. -
Senior Engineer - Managed Nand, Ufs, Fw And HwMicron Technology Mar 2019 - Feb 2022Boise, Idaho, United StatesDevelop manufacturing FW for MNAND UFS devices.Develop process for MNAND FW Development.Develop scoping and timelines for new product development. -
Senior Nand Product EngineerMicron Technology Mar 2017 - Feb 2019Boise, Idaho, United StatesLead engineer responsible for root causing and driving fix effectiveness on several NAND design issues.Responsible for building timelines and managing resources for verification of new reticles.Performed design validation using Cadence for schematic tracing and simulation.Designed and performed tests for silicon design verification using Nextest tester; included use of pico-probes for internal signal verification.
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Senior Ssd Product EngineeringMicron Technology Nov 2010 - Feb 2017SSD FW and HW Validation. Lead Engineer on Enterprise PCIe SSD project. Lead SW Infrastructure for Validation. Managed small department. Helped Develop the Async Power Cycle (Emergency Shutdown) validation test plan as well as debugged majority of failures. Debugged and wrote 8Ds for Qual Failures.
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Probe/Test EngineersMicron Technology Jun 2004 - Oct 2009Write and debug test programs for DRAM on the Teradyne and Advantest tester. Debugged HW issues on the tester and Device Interface Boys (DIBs). Debug DRAM fail modes.
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Asic/Soc Senior Test TechnicianIbm Microelectronics Division 1998 - 2001
Eric Stevens Skills
Eric Stevens Education Details
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Electrical And Electronics Engineering
Frequently Asked Questions about Eric Stevens
What company does Eric Stevens work for?
Eric Stevens works for Advantest America, Inc.
What is Eric Stevens's role at the current company?
Eric Stevens's current role is cybersecurity professional with strong background in hardware & software.
What is Eric Stevens's email address?
Eric Stevens's email address is er****@****ron.com
What schools did Eric Stevens attend?
Eric Stevens attended Boise State University, Boise State University.
What skills is Eric Stevens known for?
Eric Stevens has skills like Pcie, Perl, C++, Ssd, Firmware, Product Engineering, Python, Microcontrollers, Sata, Test Automation, Test Automation Framework, Test Development.
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Eric Stevens
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Eric Stevens
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Eric Stevens
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