Working on Datacenter TPU AI SoC chips.

- Joined as the first design engineer in the OpenTitan project.- Authored specs and wrote the RTL for several IPs(SHA2/HMAC, SPI, etc) including secure-hardened IP (SHA3/KMAC; protected against Fault-Injection attacks and 1st degree Side-Channel Analysis attacks).- Set up the development flow of the open-source hardware such as automated register generation, crossbar generation, and top-level integration tools.- Awarded 2 patents and 2 provisional patents: * Design patents: US-20220292226-A1 / US-20230099564-A1. * Pending (Provisional patents): "Secure chip-wide communication" (WO2022217260A1) "Secure serial peripheral interface communication" (WO2022226520A1)

- 7 tapeouts of PCIe & NVMe products- Integrated PCIe IPs into NVMe SSD chips. There were 4 generations of tapeouts in this product while in charge of the PCIe IP. The first was a full design, and the next 3 contained performance improvements and new features. Also participated in lab bringups and customer support. The chips were used by Amazon AWS, Sandisk, SKHynix, Kingston, and a couple of other SSD vendors.- In-charge of part of the NVMe IP. There were 3 generations of tapeouts. Implemented a new block supporting the NVMe-MI over PCIe. Also, maintained and improved existing blocks in the NVMe IP. Also participated in silicon bringups and customer support. The chips were used by Sandisk, SKHynix, Kingston, and a couple of other SSD vendors.

- 2 tapeouts in two products (SATAe, SAS controllers). - Worked on the first PCIe SSD controller in the client SSD market. The project was derived from an existing SATA SSD controller. I was the owner of the newly designed host interface (SATA Express, layered on top of PCIe). The chip was deployed in the 2013 retina Macbook Pro besides laptops from Sony, Dell, and HP. Also participated in the silicon bringups and customer support.- Worked on a 12G SAS SSD controller as one of the designers of the host interface (SCSI) before moving to Marvell.- Awarded 3 patents related to PCIe SSD: US-9304938-B2 / US-9087050-B2 / US-8990462-B2

Developed Cache Coherence Management Unit, Debugger (DAP), DDR2 SDRAM controller for High speed embedded core- Ported GNU GDB and GCC