Frederic Barbier Email & Phone Number

Nice, FR

On chip ESD protection:Specification and implementation of overall ESD strategy of CSR RF transceiver in 40nm.Design and layout of 40nm ESD clamps (power supply and analog I/O) and ESD test chips.Design of SCR in 28nm for 5V applications.Interpretation of ESD test results and failure analysis data. Provide corrective action to fix the ESD weakness.

• Implementation on silicon of the complete ESD protection network for CMOS (0.18µm) ICs (interface products for consumer applications)
• ESD design support activities for I/Os development
• Design modification and functional validation of analog IP blocks for better ESD performances
• Diagnostic and solutions proposal activities w.r.t. weaknesses observed during ESD qualification of ICs
• Development and characterizations of on-chip ESD devices according to IEC 61000-4-2 standard

• ESD design support to analog designers (design review, design guidelines, ESD device development and trainings to the design community)
• DC and RF electrical modeling activities of passive devices (design of test structures, on-chip RF characterizations and modeling works for PDK development)
• ESD design support to analog and RF I/Os libraries development in advanced CMOS (90nm to 45nm)

Thesis in collaboration with LaMIPs/CNRS Caen, France: “Improvement of the ESD protection strategy for CMOS / BiCMOS ICs”, ESD device development in CMOS (0.75µm to 0.25µm) / BiCMOS (0.25µm) technologies for I/Os and supply pins, ESD characterizations (TLP, HBM, MM and CDM) of ESD protection structures and ICs

Ph. D, Electronic, Microelectronic

Activities and Societies: Ph.D student at NXP (formely Philips semiconductors)

Bachelor Of Science (B.Sc.), Physics And Semiconductors