Greg Thompson Email & Phone Number

Helped client convert DDR tests to UVM.Improved testing of ECC functionality, including new testplan, tests, coverage analysis, and failure debug. Implemented UVM structures for model register to improve testing and checking.Led internal team to develop and deploy engineering standards, including DV coding style, shared repository usage, code reviews, DV.

Conducted verification activities as sole Q&R engineer for component integrated in nearly all Intel products.Developed verification plan, functional tests, simulation test environment, and test checkers to ensure functional quality of the configuration arrays.Documented the verification methods and tests so that other engineers could easily run existing.

Architectural developer of complex pre-silicon verification environments for simulation /emulation platform.Executed validation plans to ensure Right First Time Success for Intel products.Developed verification and coverage plans.Verified that configuration controller was properly integrated into SOC and data configuration for each SOC unit as.

Conducted system verification tests as sole verification engineer for chip configuration controller for distinct configuration data to multiple parts of the processor.Documented the configuration under test and the test results within existing tools.Wrote testplans and created checkers to run with all simulations, debugged failures, created test shortcuts.

Led the verification of Intel’s first processor-integrated memory controller and subsequent memory controllers using pre-silicon simulation methods.Planned and organized verification by working with memory controller designers and architects to plan and track schedule and progress, clarify documentation, and contribute to a robust, easily verified.

Verified new processor chip for Hyper-Threading (HT) technology, new security technologies (TXT), virtualization technology (VMX) and isochronous high-priority memory accesses.Updated testplans, wrote system-level assembly language tests, coded and analyzed test coverage conditions.Debugged failures, validated bug fixes, and shared testing methodologies.

Executed verification and bug finding, tracking and testing of three server chipsets connecting computer processor to Dram memory, other processors, and I/O devices.Wrote and maintained pre-silicon verification injectors, monitors, checkers, and tests for chipset simulations.Debugged test failures to functional bugs, spec issues, or test problems and.

Improved quality of testing blocking bad chips from sale to customers.Created new tests for checking manufacturing problems in the processor instruction caches.Created x86 assembly language self-checking manufacturing tests for Pentium processor to identify silicon problems in processor chips.

Master, Electrical And Computer Engineering

Bachelor Of Electrical And Computer Engineering, Electrical Engineering