• Design Experience of 5+ years to carryout PD flow (Netlist to GDSII) • Successfully implemented block level designs from netlist to GDSII in 3nm 5nm 12nm,14nm, and 45nm technologies.• Hands on experience and knowledge on floorplanning, placement blockages, optimization, routing congestion, & timing optimization during post CTS & post routing stages.• Essential knowledge of STA and ability to interpret timing reports for Setup and Hold analysis.• Understanding of low power concepts• Responsible for timing closure on various blocks in ECO• Fundamental knowledge of Reliability issues like EM, Cross talk, IR drop and Antenna effect.• Performed DRC clean-up, short fixing, debugging LVS issues, fixing EM violations, IR Drops on blocks.• Basic scripting skills with TCL• Experience in working different client working flow and strong ability to adapt for new work flows.• Currently working on 3nm project