Ian Davis Email & Phone Number

Designing more high performance network L3/L4 fpga based packet processors...

Designed 10GBps network L3/L4 fpga based packet processors used in Consentry Lanshield products. Handled top level, core, and external interface development for Consentry TFP & LSP ASIC’s. Created reusable self checking test environment with components for packet generation/verification, various bus masters/targets & other peripheral/memory devices. Wrote.

Responsible for design & implementation of over 10 ASIC’s and several large FPGA’s used in numerous Foundry stackable & chassis products (FastIron, BigIron, NetIron, etc...) Gained considerable experience with network packet processors, buffer managers, quality-of-service handlers, and high capacity data path design. 5 patents granted. 1 additional pending.

Cirrus Logic acquired Picopower Technology, where I worked on several ASIC chipset designs for various Intel microprocessors (386/486/Pentium/P6). Four patents granted.

Designed hardware digitizer interface ASIC. Responsible for implementation of 486 pen-based notebook system. Developed and documented custom test vector generation software.

Msee, Computer Engineering And Signal Processing

Activities and Societies: Symphonic & Rally Bands

Bsee, Computer Design

Activities and Societies: Symphonic and Rally bands