Jaydip Patel Email & Phone Number

Milpitas, Ca, Us

Milpitas, California, United States

Folsom, California, United States

Led the entire 3DXP project as a project technical leader to ensure the product data sheet meets all the spec requirements. Engage cross functionally to align product critical specs and align with project execution goals. Identify technical challenges that impact project deliverables. Align all critical stakeholders to address showstopper issues. Facilitate and drive technical topics to drive clarity and resolution for showstopper problems. Create and facilitate product architecture documentation and methodologies to drive clarity to the design execution team. Develop critical validation plans working with the section leaders to make all user and test modes are designed and validated. Manage the schematic database including top level schematic development, inter section signal clean up, hierarchy clean up, drive ERC checks & validation. Develop project milestones and trackers and report project status to critical key stakeholders.

Folsom, California, United States

Led Pathfinding for innovative new circuit solutions to reduce energy, reduce low power, improve latency and die size of 3DXP products and to develop solutions for new technology requirements. Developed novel pre-silicon power estimation methodologies to roll up accurate circuit level power more efficiently and provides efficient segmentation for debug and future innovation. Developed fullchip calculators for die size and performance estimates for early architectural decisions.

Folsom, California, United States

Led a section of Analog and Mixed Signal IC design engineers to develop Intel's 3DXP Memory. Ensured to meet section project spec goals includes power, performance, energy , functionality, validation needs are met. Monitor technical and operational challenges from other sections and create or facilitate section level architecture and methodology documentation to enable the section to meet project deliverables. Mentored post silicon device characterization and debug. Developed DOE for fullchip validation for various paths and led extensive validation from schematic level to block validation to full chip level validation including skew corner validation, temperature validation, performance spec validation, Monte Carlo, low power management, reliability, post Silicon debug capability design and validation, reliability, layout extraction, layout reviews, active power and energy calculations. Mentored several engineers to learn on the 3DXP memory technology.

Folsom, California, United States

Mixed Signal Circuit Design including Sense amplifiers, LDO Regulators, custom high density & Low Power circuit design for Intel 2D & 3D NAND Memory products.Design includes circuit design, validation, reliability analysis, die size placement, floor planning, layout interaction, analog circuit design layout guidance for matching , extraction, layout reviews Developed several circuit design & validation methodologies to improve efficiency. Most tools were developed using PERL, SKILL and shell scripting. Developed full chip analog & mixed signal model to validation NAND critical functionality, power and performance at the die level.

Folsom, California, United States

Developed Automation for Power Roll Up tools for functional blocks & custom Analog circuits using PERL, shell scripting for Intel Processors.Developed post processing scripts for data analysis mainly on power dissipation & potential improvement on functional blocks and custom Analog circuits using PERL & shell scripting for Intel Processors.

Sacramento, California, United States

Assist Dr. Perry Heedley in grading papers (exams, homework), SPICE demos and office work for Class EEE 230 (Analog and Mixed Signal IC design)

Austin, Texas Metropolitan Area

Design CMOS latch-up test structures for the Analog IO IP pad design team

Gujarat, India

FPGA Emulation using Altera's Cyclone FPGA kit, Quartus II tool and Verilog HDLProject: Implementing custom instruction for the NIOS II processorScrolling LCD display for Airports in India

Bachelor Of Science - Bs, Electronics & Communication Engineering

Activities and Societies: Gujarat University Topper in 3rd, 4th, 5th & 8th Semester Prakarsh 2006 Team Prakarsh 2007 Team FPGA Student.

Master Of Science - Ms, Electrical And Electronics Engineering

Activities and Societies: PLL2 Design Team at California State University Sacramento