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Jaydip Patel Email & Phone Number
Senior Director, Advanced Memory Development
at
Sandisk
1 work email found
@westerndigital.com
LinkedIn matched
✓ Verified Jun 2026
4 data sources
Profile completeness 100%
Current company
Role
Senior Director, Advanced Memory Development
Location
Milpitas, California, United States
Company size
Who is Jaydip Patel? Overview
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Quick answer
Jaydip Patel is listed as Senior Director, Advanced Memory Development at Sandisk, a company with 25619 employees, based in Milpitas, California, United States. AeroLeads shows a work email signal at westerndigital.com and a matched LinkedIn profile for Jaydip Patel.
Jaydip Patel previously worked as Senior Director, Advanced Memory Development at Western Digital and Senior Staff Analog Engineer at Intel Corporation. Jaydip Patel holds Bachelor Of Science - Bs, Electronics & Communication Engineering from Gujarat University.
Company email context
Email format at Sandisk
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{first}.{last}@westerndigital.com
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Profile bio
About Jaydip Patel
Experienced Leader with a demonstrated history of working in the semiconductors industry since 2006. Skilled in Microsoft Office (Power point, Excel, Outlook), Project Management, Analog & custom circuit design & Validation with several industry standard Analog building blocks, Strong Design Automation skills in Perl .With critical applications like Big Data, AI workloads, in-memory computing, and IOT, the pace of data creation is exploding and the divide between computing and memory is growing more acute. Lead a design engineering team to define advanced memory technologies.
Listed skills include Windows, Microsoft Office, English, Microsoft Word, and 10 others.
Current workplace
Jaydip Patel's current company
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Sandisk
10 roles
Jaydip Patel work experience
A career timeline built from the work history available for this profile.
Senior Director, Advanced Memory Development
Current
Apr 2022 - Present
Senior Staff Analog Engineer
Led the entire 3DXP project as a project technical leader to ensure the product data sheet meets all the spec requirements. Engage cross functionally to align product critical specs and align with project execution goals. Identify technical challenges that impact project deliverables. Align all critical stakeholders to address showstopper issues..
Jan 2018 - Apr 2022
Staff Analog Engineer
Led Pathfinding for innovative new circuit solutions to reduce energy, reduce low power, improve latency and die size of 3DXP products and to develop solutions for new technology requirements. Developed novel pre-silicon power estimation methodologies to roll up accurate circuit level power more efficiently and provides efficient segmentation for debug and.
Jan 2015 - Dec 2017
Senior Analog Design Engineer
Led a section of Analog and Mixed Signal IC design engineers to develop Intel's 3DXP Memory. Ensured to meet section project spec goals includes power, performance, energy, functionality, validation needs are met. Monitor technical and operational challenges from other sections and create or facilitate section level architecture and methodology.
Jan 2012 - Dec 2014
Analog Design Engineer
Mixed Signal Circuit Design including Sense amplifiers, LDO Regulators, custom high density & Low Power circuit design for Intel 2D & 3D NAND Memory products.Design includes circuit design, validation, reliability analysis, die size placement, floor planning, layout interaction, analog circuit design layout guidance for matching, extraction, layout reviews.
Jan 2010 - Dec 2011
Design Automation Engineer
Developed Automation for Power Roll Up tools for functional blocks & custom Analog circuits using PERL, shell scripting for Intel Processors.Developed post processing scripts for data analysis mainly on power dissipation & potential improvement on functional blocks and custom Analog circuits using PERL & shell scripting for Intel Processors.
Feb 2009 - Dec 2009
Graduate Teaching Assistant, Analog & Mixed Signal Ic Design
Assist Dr. Perry Heedley in grading papers (exams, homework), SPICE demos and office work for Class EEE 230 (Analog and Mixed Signal IC design)
Aug 2008 - Dec 2008
Cmos Pad Design Summer Intern
Design CMOS latch-up test structures for the Analog IO IP pad design team
Jun 2008 - Aug 2008
Fpga / Asic Design Engineer
FPGA Emulation using Altera's Cyclone FPGA kit, Quartus II tool and Verilog HDLProject: Implementing custom instruction for the NIOS II processorScrolling LCD display for Airports in India
Jul 2006 - May 2007
Team & coworkers
Colleagues at Sandisk
Other employees you can reach at wdc.com. View company contacts for 25619 employees →
SC
Siewli Chew
Colleague at SandiskPenang, Malaysia, Malaysia
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LC
Loh Choong Keat
Colleague at SandiskBayan Lepas, Penang, Malaysia, Malaysia
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HH
Hajjajs Hansmka
Colleague at SandiskStockton, California, United States, United States
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GM
Gangadhar Mupparapu
Colleague at SandiskLeicester, England, United Kingdom, United Kingdom
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TT
Tuan Tran
Colleague at SandiskUnited States, United States
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JL
Jessica Le
Colleague at SandiskSan Jose, California, United States, United States
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AL
Anouar Lahreche
Colleague at SandiskCasablanca-Settat, Morocco, Morocco
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HO
Hiroshi Ohsugi
Colleague at SandiskTokyo, Tokyo, Japan, Japan
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TY
Tse-Chen Yeh
Colleague at SandiskTaipei City, Taipei City, Taiwan, Taiwan, Province Of China
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BF
Bill Flynn
Colleague at SandiskSan Jose, California, United States, United States
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Siewli Chew
Colleague at SandiskPenang, Malaysia, Malaysia
View →
LC
Loh Choong Keat
Colleague at SandiskBayan Lepas, Penang, Malaysia, Malaysia
View →
HH
Hajjajs Hansmka
Colleague at SandiskStockton, California, United States, United States
View →
GM
Gangadhar Mupparapu
Colleague at SandiskLeicester, England, United Kingdom, United Kingdom
View →
TT
Tuan Tran
Colleague at SandiskUnited States, United States
View →
JL
Jessica Le
Colleague at SandiskSan Jose, California, United States, United States
View →
AL
Anouar Lahreche
Colleague at SandiskCasablanca-Settat, Morocco, Morocco
View →
HO
Hiroshi Ohsugi
Colleague at SandiskTokyo, Tokyo, Japan, Japan
View →
TY
Tse-Chen Yeh
Colleague at SandiskTaipei City, Taipei City, Taiwan, Taiwan, Province Of China
View →
BF
Bill Flynn
Colleague at SandiskSan Jose, California, United States, United States
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2 education records
Jaydip Patel education
Bachelor Of Science - Bs, Electronics & Communication Engineering
Master Of Science - Ms, Electrical And Electronics Engineering
FAQ
Frequently asked questions about Jaydip Patel
Quick answers generated from the profile data available on this page.
What company does Jaydip Patel work for?
Jaydip Patel works for Sandisk.
What is Jaydip Patel's role at Sandisk?
Jaydip Patel is listed as Senior Director, Advanced Memory Development at Sandisk.
What is Jaydip Patel's email address?
AeroLeads has found 1 work email signal at @westerndigital.com for Jaydip Patel at Sandisk.
Where is Jaydip Patel based?
Jaydip Patel is based in Milpitas, California, United States while working with Sandisk.
What companies has Jaydip Patel worked for?
Jaydip Patel has worked for Sandisk, Western Digital, Intel Corporation, California State University-Sacramento, and Nxp Acquires Freescale Semiconductor.
Who are Jaydip Patel's colleagues at Sandisk?
Jaydip Patel's colleagues at Sandisk include Siewli Chew, Loh Choong Keat, Hajjajs Hansmka, Gangadhar Mupparapu, and Tuan Tran.
How can I contact Jaydip Patel?
You can use AeroLeads to view verified contact signals for Jaydip Patel at Sandisk, including work email, phone, and LinkedIn data when available.
What schools did Jaydip Patel attend?
Jaydip Patel holds Bachelor Of Science - Bs, Electronics & Communication Engineering from Gujarat University.
What skills is Jaydip Patel known for?
Jaydip Patel is listed with skills including Windows, Microsoft Office, English, Microsoft Word, Teaching, C, Customer Service, and C++.
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