Analog Engineer
CurrentDesign analog circuits according the specifications provided.
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Jaydip Patel is listed as Analog Engineer at Intel Corporation, a company with 133841 employees, based in Sacramento, California, United States. AeroLeads shows a matched LinkedIn profile for Jaydip Patel.
Jaydip Patel previously worked as Design Automation Engineer at Intel Corporation and Teaching Assistant at Eee Department, California State University Sacramento. Jaydip Patel holds Ms, Electrical & Electronics Engineering from California State University-Sacramento.
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Entry level experience in Analog and mixed signal IC design Professional experience in CMOS circuit designProfessional experience in CMOS circuit analysis Professional experience in VLSI testing Chip lead in PLL2 team at California State University SacramentoProfessional experience in designing latch-up test structures and silicon debugging.Professional experience in FPGA emulation using Altera's Cyclone FPGA kit + Quartus II tool + SOPC builder and Professional experience in digital design using Xilinx ISESpecialties: TOPICS :CMOS circuit analysis CMOS PLL design CMOS analog comparator (Sasken comparator)Digial design & FPGA Emulation TOOLS:Mentor Graphics IC design studio Cadence Virtuoso Cadence Allegro tools OrCad PSpice Eldo HSpice ModelsimMultisimUltiboardSOPC builder (Altera)Quartus II (Altera)Xilinx ISE Synopsys VCS, Design VisionPrimetime PROGRAMMING /SCRIPTING LANGUAGESCC++Perl TCL
Listed skills include Teaching.
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Design analog circuits according the specifications provided.
General description:1. Tool support & design automation2. Flow support & Maintenance3. Flow optimization and supportWorking on 1. Scripting in C-shell, UNIX, perl and TCL.2. SQL DB management and maintenance/ scripts to upload / extract.
Assist Dr. Perry Heedley in grading papers (exams, home-works), SPICE demos and clerical work for EEE 230 - Analog and Mixed signal IC design
Design CMOS latch-up test structures for the Analog IO IP pad design team
FPGA Emulation using Altera's Cyclone FPGA kit, Quartus II tool and Verilog HDL Projects: Implementing custom instructions for the NIOS II processor Scrolling LCD display for Airports in India
Other employees you can reach at intel.com. View company contacts for 133841 employees →
Nicholas Yakubchak
Colleague at Intel CorporationChandler, Arizona, United States, United States
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Abhishek Pillai
Colleague at Intel CorporationPortland, Oregon, United States, United States
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Ilan Kor Sade
Colleague at Intel CorporationIsrael, Israel
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Glen Joyner
Colleague at Intel CorporationBeaverton, Oregon, United States, United States
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Md Shafiul Alam
Colleague at Intel CorporationKennesaw, Georgia, United States, United States
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Irene Tan
Colleague at Intel CorporationPenang, Malaysia, Malaysia
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Raghava B
Colleague at Intel CorporationSan Diego, California, United States, United States
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Gd Zhu
Colleague at Intel CorporationFolsom, California, United States, United States
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Joshua Molina Van Den Bergh
Colleague at Intel CorporationAlajuela, Costa Rica, Costa Rica
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游承桓
Colleague at Intel CorporationNew Taipei City, New Taipei City, Taiwan, Taiwan, Province Of China
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Activities and Societies: BAPS PLL2 design team at California State University Sacramento
Activities and Societies: Prakarsh 06 team Prakarsh 07 team BAPSUniversity ranker in 3,4,5,8 semester FPGA Student design engineer at.
Quick answers generated from the profile data available on this page.
Jaydip Patel works for Intel Corporation.
Jaydip Patel is listed as Analog Engineer at Intel Corporation.
Jaydip Patel is based in Sacramento, California, United States while working with Intel Corporation.
Jaydip Patel has worked for Intel Corporation, Eee Department, California State University Sacramento, Freescale Semiconductor, and System Level Solutions.
Jaydip Patel's colleagues at Intel Corporation include Nicholas Yakubchak, Abhishek Pillai, Ilan Kor Sade, Glen Joyner, and Md Shafiul Alam.
You can use AeroLeads to view verified contact signals for Jaydip Patel at Intel Corporation, including work email, phone, and LinkedIn data when available.
Jaydip Patel holds Ms, Electrical & Electronics Engineering from California State University-Sacramento.
Jaydip Patel is listed with skills including Teaching.
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