Jeffrey Thomas Email & Phone Number

Madison, WI

Participate as a Consultant in WARF’s Accelerator Program. Work with WARF staff and UW–Madison principal investigators to review the University’s CS, EE, and IT IP, provide relevant industry expertise and select promising discoveries for inclusion in the Accelerator Program and to help guide these technologies toward commercial success via licensing or.

San Jose, CA

• Hired to establish a team in San Jose, augmenting the Colorado Springs Design Center, to bring IP to Sanmina’s manufacturing capability and create IT products for Cloud Service Providers, Mega-Datacenters, and OEMs..
• Brought an Ethernet HDD JBOD to production
• The Ethernet JBOD is the first dense production JBOD supporting Seagate Kinetic HDDs
• Brought an NVMe SSD JBOD to production
• The NVMe SSD JBOD demonstrated 11M IOPS in a 2U chassis at the 2014 IDF, 14 days after receiving the first prototype boards
• Both products can be leveraged as components of a longer term, rack-scale, fabric-based, disaggregated computer system

Santa Clara, CA

• Hired to establish a new Mission Critical Scalable Server line. Joint development with team members in both US and China. Scope includes Product Definition, ASIC development, Verification, Hypervisor and System.
• Defined a Next Generation Enterprise Server Architecture – a rack-scale, PCIe fabric-based, disaggregated server
• Developed a node controller for 8-64 processor systems using Intel Xeon processors in 45 nm TSMC silicon
• Established US design processes for system development
• Led and drove both the US and China teams to work towards a shared product vision
• US leader for CFIUS (US Government Committee on Foreign Investment in the US) response involving numerous meetings with representatives from Treasury, Commerce, DoD, Justice, and various Security Agencies

Santa Clara, CA

• Hired to revitalize Sun’s UltraSPARC III (US III) design team. Stabilized the management team and organized around two teams: one for technology updates and one for architectural updates. Established the US III / US IV.
• Developed products across five process generations (150 nm – 40 nm) including the first copper based processors at Sun (US III Cu).
• Shipped US III+, USIII++, US IIIi, USIV and US IV+ to the US III / US IV roadmap.
• Developed Sun’s first multi-threaded processor (US IV).
• Released first Sun processor over 2 GHz (US IV+)
• Drove process yield and reliability issue resolution along with processor debug for the US III / US IV products.

Santa Clara, CA

• Hired to develop and lead a team to produce x86-based SOC designs for use in the emerging Information Appliance market. Got commitment from the existing senior team members, stabilized the team, reduced attrition, and.
• Defined SOC design goals and relative priorities (Schedule, Power, Cost, …).
• Established a project planning process.
• Established reference system design requirements.
• Sponsored regular cross-organizational project reviews focused on indentifying and coordinating changes to meet product goals.
• Guided the development of the design flow methodology.

Palo Alto, CA

• Hired to lead and grow a design team, responsible for development of the Alpha EV7 processor, spanning both the East and West Coasts. Maintained team focus during both the Intel and Compaq transitions. During this time.
• Defined EV7 objectives and features.
• Negotiated Rambus license agreement.
• Defined strategy for EV7 transition to a fabless semiconductor model as a part of the Intel transition.
• Revised Alpha processor roadmap.
• Responsible for review and revision of Alpha development process.

San Jose, CA

• Formed a start-up design team of 26 engineers who taped out a 533 MHz BiCMOS PowerPC microprocessor in two and a half years, including porting the design to a new semiconductor fab in five months (which required the.
• Focused on hiring to increase the engineering staff from an initial total of 12 to a final total of 45.
• Resolved product content issues and developed metrics to measure progress to targets.
• Established a custom BiCMOS design process and determined which software tools would be required to be developed in-house.
• Three all-layer tapeouts and two metal-only tapeouts handled in one year.
• Led team during final validation phase, resulting in a tight team effort that produced clean full chip LVS and DRC runs 21 days after the first attempt.

Fremont, CA

• Created Amdahl's first external, CMOS, RISC microprocessor-based development team and operated it as a start-up separate from Amdahl. Managed, with hands-on technical involvement, all ASIC, system mechanical, power.
• Developed a project planning process using continuous feedback, allowing development teams to improve schedule accuracy.
• Defined and implemented a development and testing methodology spanning ASIC development, software development, simulation, and engineering model bring-up achieving 19 ASICs and 13 boards functional at first release.
• Established design requirements ensuring a manufacturable and serviceable product while allowing the product to be manufactured using outside vendors at 10% of normal manufacturing cost.
• Introduced a concurrent engineering process resulting in no manufacturing show-stoppers on initial build machines and few manufacturability design changes after design release.

Sunnyvale, CA

• Bring-Up Testing Manager: 1985 - 1989Directed testing of two mainframe computer systems (5890, 5990) involving long term planning, developing specific test procedures, and day-to-day involvement with bug resolution..
• Merged three testing organization's separate plans into a unified test plan eliminating redundancy and saving six months of testing. Technical Change Manager: 1984 - 1989 Ensured products being released (5890, 5990).
• Developed and executed a plan that reduced ASIC turn-around time from two weeks to five days.
• Established and managed a development and release process resulting in the release of 450 working ASICs over one year.
• Created a manufacturing process allowing engineering changes to be cut into production as late as two weeks before shipment. This process reduced the test and release time for changes by over four weeks.Technical.
• Architected a virtually addressed, split I and D cache and defined the coherency protocol.

Electrical Engineering

part-time

Bsee, Electrical Engineering

Graduated with Honors in three years