Ji Chen Email & Phone Number

Santa Clara, California, Us

Santa Clara, California, Us

SoC design integration and DV lead for MI100/MI200 AI/HPC GPUs.Worked together with IP/SoC architects to completed feature alignment and integration, to scope test scenarios and coverage for all SoC new features, and to set performance verification test scenarios and KPIs.Led CPU/GPU coherency test planing, and PCIe/multi-socket performance analysis and optimization.

Santa Clara, California, Us

Built AMD Beijing GPU function DV team.Led overall SOC DV of Vega12 GPU, ensured successful tapeout in a highly compacted schedule.Led DFx DV of Vega10 GPU with brand new SOC architecture. Drove high design and ATE pattern quality.

Santa Clara, California, Us

Built AMD Beijing GPU DFx DV team.Led DFT DV of industry 1st HBM-enabled GPU "Fiji", owned testplan for HBM DFT and oversaw full chip DFT DV execution.Ensured high-quality delivery of HBM test features and production test patterns.

Santa Clara, California, Us

In Xbox One APU project, owned DFT security DV from plan to coverage, prepared testplan for Design-for-Debug.

Conducted a small DV team constructing a VMM-based verification lib/env and HW/SW infrastructure, and to complete verification of a 20Gbps L4 session-based packet forwarding FPGA.

Ca

Digital logic DV Engineer in Enterprise Division, participated in verification of core datapath FPGA in VSP9000 routing switch.

Master, Telecom

Bachelor, Ee

Education record