Jim Blanchard Email & Phone Number

Phoenix, Az, Us

Manage a Quality Assurance Lab.

• Instrumental for the design of the Test Interface Unit (TIU) for the CMT tester. This entailed getting the required specifications and requirements for the specific device to be tested. Detailed the build specification for the TIU. Used CAD tools (Cadence Allegro) to analyze the schematics to ensure that the design specification was followed. • Using PERL, generate scripts to modify Test Vectors. Wrote ATE Test Software by generating test vectors, performed validation on simulation models, and debugged any issues on these models. Compiled the C++ tester software using Visual Studio. Implemented the software vectors into the main test program. • Debugged the C++ ATE test software vectors using Visual Studio.net & custom software developed by Intel. After debugging the vectors in simulation, debug these vectors using silicon on a tester.• Optimized ATE test vectors and programs through PERL script characterization and other techniques.• Tested large quantities of Integrated Chipsets (Combined Northbridge & Southbridge) for a computer, and an Integrated Microprocessor (Microprocessor, Northbridge, Southbridge, GigaBit-E, etc) to verify that the ATE tester software was reliable, and didn’t create false rejects. This was repeated on numerous testers. This was to guarantee the Repeatability & Reproducibility to ensure successful manufacturing start-up.• Work as a part of a team to determine the key milestones, receivables, deliverables of the projects assigned. • Knowledge was acquired on different interfaces to successfully generate test vectors and to do Compliance testing. The interfaces that were tested were: USB, SATA, PCI-e, & DDR.• Worked as part of a cross-site, multinational team to be the first group at Intel to develop an integrated processor.• Delivered Data Sheet Characterization Reports that were required by a major customer. This report is required to summarize the data to illustrate Intel’s compliance to data sheets.

• Ensured that the products being delivered to the customer’s DBS / MMDS set top box manufacturing plant in Juarez, Mexico met with the expectations of their manufacturing community. • Corrective actions issued by ST were explained to the pertinent personnel at the customer’s manufacturing plants. This involved taking complex ideas / solutions to people that sometimes didn’t have a technical background.• Effected change at the customer’s manufacturing line by translating complicated concepts as given by ST’s divisions into actionable items at the manufacturing plant.• Worked with the Divisions to help them understand the issues that the customer experienced during the manufacture of the digital set top boxes which allowed for improved corrective actions based on the customer’s usage model.• Designed Qualification Packs to be submitted to the customer for the qualification of new products that were being designed in new products improving ST’s TAM at the customer.• Designed and implemented a worldwide database using an Access front-end and an Oracle back-end. This database was used to track and forecast the sales growth of numerous customers. The database was used to track the whole Consumer Business Segment at ST (In excess of $500M).• Designed a database to help track and store all the needed information for Qualification samples. Tracked this information from the initial request from the customer to the final customer approval to document product qualifications.

• Developed and implemented high yield electronic circuit designs (schematics) for the DBS and MMDS Digital Set Top Boxes as a part of a design team, which ensured an easy to manufacture The Digital Set Top Boxes in the Mexican assembly plant.• Debugged units. This involved using various pieces of lab equipment (Oscilloscopes, Logic Analyzers, Meters, JTAG Testers, etc). When the Issue was found, desoldered the failing component, and soldered a replacement component in place.• Analyzed ICs that have failed in various Digital Set Top Boxes (DBS and MMDS) on the manufacturing line in Juarez, Mexico. This was to determine and track the failure trends or yield losses of ICs so that the defect rate could be reduced thus maximizing the yield.• Implemented various corrective actions to lower the false pull rate of ICs from the main boards and completed units on the line to maximize production yields.• Performed Destructive Physical Analysis. This was to determine if ICs passed Thomson’s standards. This was to ensure the quality and reliability of the ICs before they were used in TV, DBS, MMDS and DVD units. Numerous defects were detected and reported back to the supplier, for their corrective actions.

• Testing was performed on ICs and discrete components per MIL-STD-883, MIL-STD-750, and applicable manufacturer specifications to determine if the component was a confirmed failure. • The failure mechanisms in Electronic ICs and assemblies were characterized.• Destructive Physical Analysis (DPA) was performed per MIL-STD-1580 and other specifications. This was done to ensure the quality and reliability of the components before use on the manufacturing line.• A Failure Analysis Technician is exposed to numerous IC technologies (e.g. TTL, CMOS, ASIC, and Gate Array) as well as different types of discrete components. Various Failure Analysis Techniques used: Physical Analysis; Electrical Analysis; Microscopy, Micro-probe, Plasma Etch; SEM & E-Beam (JEOL) Examination; Chemical De-Processing.

Bachelor Of Science, Electrical Engineering

Associates Degree, Electrical Engineering Technology