Hsin I (Julius) Li Email & Phone Number
@motional.com
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Who is Hsin I (Julius) Li? Overview
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Hsin I (Julius) Li is listed as Assembly Design Rule Owner at Intel, a with 114813 employees, based in Stuttgart, Baden-württemberg, Germany. AeroLeads shows a work email signal at motional.com and a matched LinkedIn profile for Hsin I (Julius) Li.
Hsin I (Julius) Li previously worked as Fellow Process Integration Engineer at Q.Ant and Semiconductor Component Engineer at Motional. Hsin I (Julius) Li holds Doctor Of Philosophy (Ph.D.), Physics from Penn State University.
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AeroLeads found 1 current-domain work email signal for Hsin I (Julius) Li. Compare company email patterns before reaching out.
About Hsin I (Julius) Li
A semiconductor device engineering professional with 15 plus years in IC developing and manufacturing environments. Skills include SPICE modeling of active and passive devicesfrom device level to interconnect, device design/improvement with TCAD simulation, hands-on experience on crystal surface preparations and characterizations, and maintaining Ultra High Vacuum system. An experienced engineer that can work on both device modelings and hands-on experiments and like to embrace technology challenges of semiconductor device development.Specialties: Crystal surface preparation, characterization, Surface structure determinations, Semiconductor device characterization, SPICE modeling,TCAD simulation.
Listed skills include Physics, Experimentation, Fortran, Simulations, and 12 others.
Hsin I (Julius) Li's current company
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Hsin I (Julius) Li work experience
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Fellow Process Integration Engineer
Semiconductor Component Engineer
✜ Provided consultation to internal stakeholders regarding incoming semiconductorfield application issues, collaborating with vendors to update silicon and streamlinequalifications..✜ Collaborated with external semiconductor design/manufacturing partners andinternal System Architects to devise AI SoC solutions aligning with performance,quality, budget, and timeline criteria.✜ Conducted market research and interviews with current AI semiconductor providers,offering… Show more ✜ Provided consultation to internal stakeholders regarding incoming semiconductorfield application issues, collaborating with vendors to update silicon and streamlinequalifications..✜ Collaborated with external semiconductor design/manufacturing partners andinternal System Architects to devise AI SoC solutions aligning with performance,quality, budget, and timeline criteria.✜ Conducted market research and interviews with current AI semiconductor providers,offering insights to guide the development of Motional’s future-generation AI chipsolutions.✜ Evaluated hardware and software maturity through AI chip architecture comparisonand development kit testing. Show less
Scribe Design Engineer
✜ Led a team of 5 structure designers in pioneering advanced ferroelectric memory teststructure design, supporting cutting-edge projects for next-generation memory.✜ Collaborated with Integration and Cell design teams to develop advanced ferroelectricmemory test structures, incorporating innovative device concepts and materials intofeasible process plans.✜ Designed test chips and structures to evaluate the electrical and physical propertiesof new materials and novel… Show more ✜ Led a team of 5 structure designers in pioneering advanced ferroelectric memory teststructure design, supporting cutting-edge projects for next-generation memory.✜ Collaborated with Integration and Cell design teams to develop advanced ferroelectricmemory test structures, incorporating innovative device concepts and materials intofeasible process plans.✜ Designed test chips and structures to evaluate the electrical and physical propertiesof new materials and novel stacks.✜ Investigated device physics and process integration, analyzing their impact on newmaterials and novel stacks, and contributing to the debugging of inline and final testresults.✜ Addressed design requirements considering photo overlay and printing limitations,as well as process-related issues such as CMP and defectivity, to ensure module-leveltestability development and compliance with DRC/LVS standards.✜ Planned and positioned test modules for frames and test dies, conducted DFMverification of mask data, and managed tapeout handling/sign-offs. Show less
Sr. Process Integration Engineer
✜ Worked with global partners and customers to qualify new products and improveproduct yields.✜ Spearheaded process control and device optimization for 0.18 μm Logic andMixed-Signal products, including the creation of new tapeout processes.✜ Successfully managed the transfer of 0.18 μm 1.8/5V Mixed-Mode technology fromTSMC mother Fab to ensure seamless production.✜ Led a TCAD simulation task force dedicated to resolving Fab issues and constructingsimulation templates… Show more ✜ Worked with global partners and customers to qualify new products and improveproduct yields.✜ Spearheaded process control and device optimization for 0.18 μm Logic andMixed-Signal products, including the creation of new tapeout processes.✜ Successfully managed the transfer of 0.18 μm 1.8/5V Mixed-Mode technology fromTSMC mother Fab to ensure seamless production.✜ Led a TCAD simulation task force dedicated to resolving Fab issues and constructingsimulation templates for Flash and Mixed-Mode devices.✜ Utilized TCAD process and device simulation techniques for CMOS and Flashdevices, aiding in device design and process issue debugging, and contributed to thedevelopment of high-voltage embedded Flash processes. Show less
Teaching/Research Assistant
✜ Led recitation sessions and supervised laboratory activities for calculus-basedElectricity and Magnetism courses, as well as algebra-based Introductory Physicscourses.✜ Conducted characterization and analysis of crystal surfaces and their interactionswith adatoms as part of the Surface Science Group at Penn State.
Principal Engineer Spice R&D
✜ Led compact SPICE modeling efforts for 0.13 μm and 90 nm MOSFET and passivedevices, leveraging BSIM3 model.✜ Specialized in interconnect modeling of backend RC, contributing to the optimizationof signal transmission and routing.✜ Pioneered the development of interconnect simulation software and modelingmethodologies, establishing them as the standard tools and procedures for post 0.13μm technology releases.✜ Played a key role in TCAD development and modeling for… Show more ✜ Led compact SPICE modeling efforts for 0.13 μm and 90 nm MOSFET and passivedevices, leveraging BSIM3 model.✜ Specialized in interconnect modeling of backend RC, contributing to the optimizationof signal transmission and routing.✜ Pioneered the development of interconnect simulation software and modelingmethodologies, establishing them as the standard tools and procedures for post 0.13μm technology releases.✜ Played a key role in TCAD development and modeling for 0.18 μm embedded DRAMdevices, enhancing device performance and reliability. Show less
Device Engineer R&D
✜ Successfully developed cell and peripheral devices for 0.19 µm DRAM technology with TCADsimulation support.✜ Delivered interconnect modeling for 0.19 µm DRAM technology.
Test Development Engineer
✜ Developed magnetic parametric testing method for hard drive disk production.✜ Responsible for Guzik characterization of magnetic film and head performance.Academia
Colleagues at Intel
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Rhonda Thompson
Colleague at IntelLaveen, Arizona, United States
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Tidhar Suchard
Colleague at IntelHaifa District, Israel
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Abhijit Chinchore
Colleague at IntelBeaverton, Oregon, United States
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Alif Noor
Colleague at IntelPenang, Malaysia
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Avery Payne
Colleague at IntelPortland, Oregon Metropolitan Area, United States
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Maria Fernandez
Colleague at IntelPortland, Oregon, United States
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Liam Frost
Colleague at IntelTrim, County Meath, Ireland
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Kai C.
Colleague at IntelSanta Clara, California, United States
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Sebastian Winkel
Colleague at IntelLos Altos, California, United States
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Lior Cohavi
Colleague at IntelNorth District, Israel
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Hsin I (Julius) Li education
Doctor Of Philosophy (Ph.D.), Physics
Ms, Physics
Bs, Physics
Frequently asked questions about Hsin I (Julius) Li
Quick answers generated from the profile data available on this page.
What company does Hsin I (Julius) Li work for?
Hsin I (Julius) Li works for Intel.
What is Hsin I (Julius) Li's role at Intel?
Hsin I (Julius) Li is listed as Assembly Design Rule Owner at Intel.
What is Hsin I (Julius) Li's email address?
AeroLeads has found 1 work email signal at @motional.com for Hsin I (Julius) Li at Intel.
Where is Hsin I (Julius) Li based?
Hsin I (Julius) Li is based in Stuttgart, Baden-württemberg, Germany while working with Intel.
What companies has Hsin I (Julius) Li worked for?
Hsin I (Julius) Li has worked for Intel, Q.Ant, Motional, Micron Technology, and Tsmc.
Who are Hsin I (Julius) Li's colleagues at Intel?
Hsin I (Julius) Li's colleagues at Intel include Rhonda Thompson, Tidhar Suchard, Abhijit Chinchore, Alif Noor, and Avery Payne.
How can I contact Hsin I (Julius) Li?
You can use AeroLeads to view verified contact signals for Hsin I (Julius) Li at Intel, including work email, phone, and LinkedIn data when available.
What schools did Hsin I (Julius) Li attend?
Hsin I (Julius) Li holds Doctor Of Philosophy (Ph.D.), Physics from Penn State University.
What skills is Hsin I (Julius) Li known for?
Hsin I (Julius) Li is listed with skills including Physics, Experimentation, Fortran, Simulations, Characterization, R&D, Cmos, and Surface Chemistry.
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