Lily Tam Email and Phone Number

- Principal Hardware Engineer, Oracle Corp. (Present - 03/31/2010)1. Statistical analysis and tool developement to help mitigate impact of PVT in FIN10 nodes and beyond.2. Research and study current EDA methodology and best practices in the area of timing, power, EM/IR, extraction, noise, circuit simulation, and foundry device processing. Presented a comparative study of planar MOSFET vs FinFETs to help guide fellow methodology engineers on what to expect as the industry move beyond 20nm process technology and potential impacts on all in-house and industry EDA tool developments(July,2012).3. Provide support and guidance on critical path cutting tool used for early timing analysis and internal transistor level timer for SRAM design team for both 20nm and 28nm projects. Setup and maintain block level regression and act as a liaison between design and developer teams to ensure wide tool acceptance by ensuring all critical features are included and enhancements are prioritized and delivered accordingly.4. Provide support and guidance on timing methodology of internal gate-level timer tool used for two successfully taped out 28nm design projects. Setup and maintain proper block level tool regression to ensure and expedite any enhancement requests and bug fixes. Monitor timer performance and memory usage data and work with developers to develop solutions to ensure tool can handle future processor designs in the road map with improved run time and memory foot prints.

1. Managing top level integration of 28nm test chip and completed gds delivery on schedule. Finish top level DRC/LVS layout edits and metal fill myself to quickly ensure timely completion of deliverables. Setting power grid and intermediate deliverables for the team to ensure a smooth top level integration.2. Custom designed, implemented, and verified 18x18 multiplier and Block RAM using asynchronous handshake techniques for a 1.5GHz FPGA in 65nm technology node, thus far the fastest FPGA chip on the planet. Logic is designed using in-house asynchronous description language. The designs are converted directly to spice netlist for layout implementation and simulation. Functional verification is handled through an in-house logic simulation tool designed to handle the event driven nature of asynchronous designs. Assisted with silicon bring up and debugging post tapeout. Chips have passed all post silicon qualification and production testing and ready for ramp up. They are also already being sampled by customers.3. Designed, implemented, and verified a radiation hardened asynchronous block RAM tile and 4-input asynchronous LUT tile for the second chip, first rad-hard chip of the company. Taped out on schedule. Rad-hard technique in asynchronous domain is eloquent and doesn't not require majority rule to over come SEU.

Custom circuit & logic designer, Broadband Processor DivisionProject: Broadcom/Sibyte latest MIPS SOC(BCM1400s) and GMIPS 1.Designed shifter/shuffle block(dynamic and static logic) from microarchitecture to RTL to layout using semi-custom methodology. Dynamic design speedup is carefully balanced by the need to limit potential noise sources to dynamic nodes and static-izer used to interface with the static stage.  Custom placed and automatically routed. Passed RTL regression and fixed all known functional bugs. Performed schematic/rtl LEC, layout DRC/LVS, met timing and area targets, passed clock and noise analysis and DFT verification steps. 2.Developed pass-gate(low DFT coverage) and nand implementation muxes for global standard cell library. 3.Feasibility studies of Broadcom's next generation semi-custom MIPS SOC by resimulating glitch buses and arrays timing paths in new 65nm process to ensure designs meet new timing target. 4.Developed perl scripts to speed up spice file generations of postlayout designs using nets from only the critical path(s), thus speeding up extraction and spice run time for postlayout timing verification. Used on jcache and dcache postlayout timing verification with spice.

1. Circuit design engineer on UltraSparc VI project (4/2001 ~ 12/2004) Successfully taped out UltaSpac V 2.1GHz, 90nmWorked from microarchitecture to RTL to layout implementation, performed RTL verification under stand-alone self test environment and random regression.  Implementation responsibilities include design equivalency, layout floorplan, place & route, post layout verifications such as timing, noise, EM/IR, DFT, clock distribution, power consumption analysis etc at both local and cluster levels. Designed and implemented 64-bit graphic adder and 64-bit multiplier. Multiplier used booth encoding and adder used Ling's equation and binary tree carry generation. Synthesized FGU global control blocks. Power optimization include clock/thread gating and limit LVT usage. Developed methodology for in-house transistor level classification and timing tool. 2. Integration Engineer on an embedded Sparc derivative (6/1999-4/2001)Successfully taped out Sun's first embedded low-end Sparc processor project(0.13um, 550MHz).