Lloyd Smith

Lloyd Smith Email and Phone Number

Failure Analysis Engineer at Infineon Technologies @ Infineon Technologies
germany
Lloyd Smith's Location
Livonia, Michigan, United States, United States
Lloyd Smith's Contact Details

Lloyd Smith work email

Lloyd Smith personal email

About Lloyd Smith

Failure Analysis Engineer - Advanced Technology Development - Globalfoundries / IBM Microelectronics► Guided, directed, and instructed fellow engineers and technicians on instrument use, localization strategies, and results interpretation.► Provided concise reporting and rapid feedback to the appropriate engineering and development communities.► Experience with Optical Microscopy, Electron Microscopy, Focus Ion Beam (single and dual beam), sample preparation, sample decoration, and inverted TEM lamella creation.► Hands-on isolation of defects using electrical, physical, and optical isolation techniques including bench testing, OBIRCh, and in-situ SEM probe systems.Email: lloyd.smith.1119@gmail.com

Lloyd Smith's Current Company Details
Infineon Technologies

Infineon Technologies

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Failure Analysis Engineer at Infineon Technologies
germany
Website:
infineon.com
Employees:
19449
Lloyd Smith Work Experience Details
  • Infineon Technologies
    Sr Failure Analysis Engineer
    Infineon Technologies 2019 - Present
    Livonia, Michigan, United States
    Hands-on inspection, confirmation, and analysis of customer returns. Optical/IR inspection, SEM, SAM, curve tracing, layout inspection, fractography, and chemical/laser/plasma decapsulation.Generated reports and direct feedback of results to internal and external customers. Explained methodology, reasoning, techniques, and conclusions to end-users with varying levels of technical expertise. Gave presentations on semiconductor manufacturing to external and internal… Show more Hands-on inspection, confirmation, and analysis of customer returns. Optical/IR inspection, SEM, SAM, curve tracing, layout inspection, fractography, and chemical/laser/plasma decapsulation.Generated reports and direct feedback of results to internal and external customers. Explained methodology, reasoning, techniques, and conclusions to end-users with varying levels of technical expertise. Gave presentations on semiconductor manufacturing to external and internal customers.Directly responsible for the wet-lab environment, including: all facilities matters, chemical selection, approval, safety, and waste related activities. Show less
  • Globalfoundries
    Failure Analysis Engineer
    Globalfoundries 2015 - 2020
    Support for 7nm and 14nm development programs with KERF failure analysis. Root-cause defect identification by hands-on laboratory techniques (test verification, electrical characterization, optical localization, sample delayering, SEM inspection, FIB sectioning). Reported and presented analysis results to the relevant process communities for yield improvement and development goals. Work with a close-knit cadre of engineers and technicians to collaboratively develop methods and procedures for… Show more Support for 7nm and 14nm development programs with KERF failure analysis. Root-cause defect identification by hands-on laboratory techniques (test verification, electrical characterization, optical localization, sample delayering, SEM inspection, FIB sectioning). Reported and presented analysis results to the relevant process communities for yield improvement and development goals. Work with a close-knit cadre of engineers and technicians to collaboratively develop methods and procedures for defect identification on leading edge semiconductor devices. Show less
  • Ibm
    Failure Analysis Engineer
    Ibm Jan 2013 - Jun 2015
    Hopewell Junction, Ny
    Lead FA engineer working with a team of technicians to support the IBM 14nm FEOL/MOL product development. Responsible for driving and guiding the FA activities for root cause analysis (Fault Isolation, de-processing, nanoprobing, cross sectioning, and high resolution elemental TEM imaging).Preformed hands-on analysis in the lab including layer-by-layer planar de-processing of semiconductor chips using wet etch, dry etch, and finger polishing. Bench micro probing for fault… Show more Lead FA engineer working with a team of technicians to support the IBM 14nm FEOL/MOL product development. Responsible for driving and guiding the FA activities for root cause analysis (Fault Isolation, de-processing, nanoprobing, cross sectioning, and high resolution elemental TEM imaging).Preformed hands-on analysis in the lab including layer-by-layer planar de-processing of semiconductor chips using wet etch, dry etch, and finger polishing. Bench micro probing for fault confirmation, characterization, and isolation using Agilent, Keysight, and Keithly parametric analyzers. Fault Isolation Techniques such as OBIRCh, PEM, and voltage contrast.Acted as defect and yield pareto owner, presented and explained key yield detractors in weekly process integration and characterization meetings to drive yield improvement and determine necessary follow-up. Developed new failure analysis methods and techniques, trained/mentored engineers and technicians. Show less
  • Ibm
    Failure Analysis Technician
    Ibm Mar 2003 - Dec 2012
    Hopewell Junction, Ny
    Support for KERF failure analysis on 14nn SOI FEOL2/MOL. Responsibilities included: electrical characterization, localization, isolation, deprocessing, analysis, and reporting of results. Analysis techniques routinely include: electrical interpretation, OBIRCH, photon emission, FIB voltage contrast/macro engineering, and cross sectioning (cleave, polished, FIB, and STEM). The position requires continual contact with the characterization group to prioritize work along with the presentation of… Show more Support for KERF failure analysis on 14nn SOI FEOL2/MOL. Responsibilities included: electrical characterization, localization, isolation, deprocessing, analysis, and reporting of results. Analysis techniques routinely include: electrical interpretation, OBIRCH, photon emission, FIB voltage contrast/macro engineering, and cross sectioning (cleave, polished, FIB, and STEM). The position requires continual contact with the characterization group to prioritize work along with the presentation of results to the appropriate engineering groups. Prior to the 14nm node, I supported the 65nm, 45nm, 32nm, and 22nm technology nodes in the same capacity. Show less
  • Parity Teltech For Ibm Microelectronics
    Failure Analysis Technician / Sem Technician
    Parity Teltech For Ibm Microelectronics Apr 2001 - May 2002
    Hopewell Junction, Ny
    As a contractor prepared, cleaved, mechanical-polished, and micro-graphed samples for Scanning Electron Microscope (SEM) analysis. Worked on all technologies (DRAM and logic) in the Physical Failure Analysis Labs of IBM’s 200mm ASTC and 300mm FAB. Cleaved bulk arrays, specific macros, and discrete devices. Hand-polished thru large arrays, discrete devices, single cell defects, isolated vias, FIB marked junctions, etc. Used plasma highlight, wet etch decoration, and deposition tools for sample… Show more As a contractor prepared, cleaved, mechanical-polished, and micro-graphed samples for Scanning Electron Microscope (SEM) analysis. Worked on all technologies (DRAM and logic) in the Physical Failure Analysis Labs of IBM’s 200mm ASTC and 300mm FAB. Cleaved bulk arrays, specific macros, and discrete devices. Hand-polished thru large arrays, discrete devices, single cell defects, isolated vias, FIB marked junctions, etc. Used plasma highlight, wet etch decoration, and deposition tools for sample preparation (ex. Chrome, TEOS, Quartz, DE100, etc.). SEMs included the Hitachi 800, 4100,4500, 4700, 5000, 5000H, and 5200. Show less
  • Dominion Semiconductor
    Integration Co-Op
    Dominion Semiconductor Sep 1999 - Jun 2000
    Manassas, Va
    Worked with the Process Change Review Board (PCRB) and Integration/ Process Engineering. Defect analysis, data retrieval, SPC charting, wafer inspection with JEOL SEM and Leica workstations, sorting and scrapping, conducting experiments in the FAB for yield improvement, etc

Lloyd Smith Skills

Failure Analysis Semiconductor Failure Analysis Scanning Electron Microscopy Semiconductors Characterization Semiconductor Process Technology Research And Development Fib Semiconductor Fabrication Integrated Circuits Process Integration Sports Photography

Lloyd Smith Education Details

Frequently Asked Questions about Lloyd Smith

What company does Lloyd Smith work for?

Lloyd Smith works for Infineon Technologies

What is Lloyd Smith's role at the current company?

Lloyd Smith's current role is Failure Analysis Engineer at Infineon Technologies.

What is Lloyd Smith's email address?

Lloyd Smith's email address is ll****@****ail.com

What schools did Lloyd Smith attend?

Lloyd Smith attended Western Connecticut State University.

What skills is Lloyd Smith known for?

Lloyd Smith has skills like Failure Analysis, Semiconductor Failure Analysis, Scanning Electron Microscopy, Semiconductors, Characterization, Semiconductor Process Technology, Research And Development, Fib, Semiconductor Fabrication, Integrated Circuits, Process Integration, Sports Photography.

Who are Lloyd Smith's colleagues?

Lloyd Smith's colleagues are Roberto Jose, Atiah Ishak, Hendri Tenis Agasi Siburian, Leticia Rodriguez, Gooveen Subramaniam, Wei Choong Chong, Fernando Juarez.

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