Mar 2018 - Present
AeroLeads people directory · profile
Mark Mercado Email & Phone Number
Principal Engineer
at
Western Digital
1 work email found
@hgst.com
1 phone found area 312
LinkedIn matched
✓ Verified July 2026
4 data sources
Profile completeness 100%
Current company
Role
Principal Engineer
Location
San Francisco Bay Area, United States
Company size
Who is Mark Mercado? Overview
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Quick answer
Mark Mercado is listed as Principal Engineer at Western Digital, a with 22750 employees, based in San Francisco Bay Area, United States. AeroLeads shows a work email signal at hgst.com, phone signal with area code 312, and a matched LinkedIn profile for Mark Mercado.
Mark Mercado previously worked as Professional Development at University Of California, Santa Cruz and Senior Engineer, Thin Film Development at Hgst. Mark Mercado holds Master Of Science (M.S.), Mechanical Engineering from Stanford University.
Company email context
Email format at Western Digital
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{first}.{last}@hgst.com
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AeroLeads found 1 current-domain work email signal for Mark Mercado. Compare company email patterns before reaching out.
Profile bio
About Mark Mercado
Innovative, capable and reliable Stanford graduate with 10+ years of product development experience in the high tech industry. Extensive experience in development and transfer from prototype phase to high volume manufacturing. Broad experience in statistical process control, DOE, data mining and machine learning with Python, R, SAS and SQL. Experience as a Program Manager with excellent communication and technical presentation skills.Three patents in materials and process for the data storage industry for thin film deposition with Chemical and Physical Vapor Deposition (CVD and PVD) systems. .
Listed skills include Program Management, Design Of Experiments, Integration, Thin Film Development, and 15 others.
Current workplace
Mark Mercado's current company
Company context helps verify the profile and gives searchers a useful next step.
Western Digital
5 roles
Mark Mercado work experience
A career timeline built from the work history available for this profile.
Professional Development
University Of California, Santa Cruz
Data Analysis Certificate ProgramEnhance process engineering skills with Data Analysis Certificate (1Q2018) with projects and coursework in Python, R, SQL, Data Mining, Machine Learning, IoT, Kafka, Spark and AWS distributed cloud computing.
Oct 2016 - Mar 2018
Senior Engineer, Thin Film Development
Hgst
Enabled first-to-market product releases of industry’s highest capacity storage products, over a 10+ year period, by continuous innovative development and seamless transfer of thin film media technology to our high volume manufacturing facility.• Achieved design breakthroughs by utilizing experience in process development, optimization, metrology and equipment for Chemical and Physical Vapor Deposition (CVD and PVD) systems.• Opened new development space by inventing, patenting and productizing novel plasma polish etch process (9,159,353) for both PVD (magnetron sputtering) and CVD hardware. Led team to implement this new technology across all product segments (mobile, desktop and server)• Systematically improved product designs utilizing factorial design of experiments (DOE) process and analyzing with JMP statistical software.• Increased rate of development and reduced data analysis time by creating Visual Basic programs for automatic trending of performance parametrics versus input design parameters.• Allowed on schedule qualification of the new media designs by converting pilot-line sputter tools to high volume manufacturing tools and implementing SPC with automatic trend charting of key build parameters.
Jan 2012 - Jul 2016
Senior Engineer, Thin Film Development
Developed thin film stack architecture, magnetic and non-magnetic alloys and sputter process for enterprise, mobile and desktop storage media products.• Allowed first-to-market release of new storage products by developing, patenting and productizing innovative onset layer (9,412,404) for thin film media grain isolation.• Verified design conformance and isolated build anomalies by developing SAS and SQL code for data mining and trending of sputter process data.• Hands on experience with XRR, XRD, XRF, Ellipsometry and VSM.• Directed and utilized AES, XPS, SEM/EDX, TEM, TOFSIMS, AFM and Optical Microscopy.
Jan 2003 - Jan 2012
Staff Engineer (Program Manager)
Staff Engineer (Program Manager) OEM Storage MediaEstablished first qualification of IBM magnetic media into external customer storage products. Managed key engineers and our overseas manufacturing team.
Jan 1999 - Jan 2003
Team & coworkers
Colleagues at Western Digital
Other employees you can reach at wdc.com. View company contacts for 22750 employees →
SP
Siriluk Pichayaanankul
Colleague at Western DigitalBangkok, Bangkok City, Thailand
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TC
Tharika Chienarom
Colleague at Western DigitalBangkok, Bangkok City, Thailand
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RB
Robert Briner
Colleague at Western DigitalLivermore, California, United States
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MI
Mohd Iqbal Alias
Colleague at Western DigitalKulim, Kedah, Malaysia
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BY
Brian Young
Colleague at Western DigitalTracy, California, United States
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JE
Joseph Edquid
Colleague at Western DigitalHaven, Kansas, United States
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AD
Ashok Desai
Colleague at Western DigitalThousand Oaks, California, United States
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SL
Shivaraju L
Colleague at Western DigitalBengaluru, Karnataka, India
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ZL
Zhizhen Li
Colleague at Western DigitalChina
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KG
Khartik Ghaneson
Colleague at Western DigitalPerak, Malaysia
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Siriluk Pichayaanankul
Colleague at Western DigitalBangkok, Bangkok City, Thailand
View →
TC
Tharika Chienarom
Colleague at Western DigitalBangkok, Bangkok City, Thailand
View →
RB
Robert Briner
Colleague at Western DigitalLivermore, California, United States
View →
MI
Mohd Iqbal Alias
Colleague at Western DigitalKulim, Kedah, Malaysia
View →
BY
Brian Young
Colleague at Western DigitalTracy, California, United States
View →
JE
Joseph Edquid
Colleague at Western DigitalHaven, Kansas, United States
View →
AD
Ashok Desai
Colleague at Western DigitalThousand Oaks, California, United States
View →
SL
Shivaraju L
Colleague at Western DigitalBengaluru, Karnataka, India
View →
ZL
Zhizhen Li
Colleague at Western DigitalChina
View →
KG
Khartik Ghaneson
Colleague at Western DigitalPerak, Malaysia
View →
3 education records
Mark Mercado education
Master Of Science (M.S.), Mechanical Engineering
Data Analytics, Certificate Program
Bachelor Of Science (B.S.), Mechanical Engineering
FAQ
Frequently asked questions about Mark Mercado
Quick answers generated from the profile data available on this page.
What company does Mark Mercado work for?
Mark Mercado works for Western Digital.
What is Mark Mercado's role at Western Digital?
Mark Mercado is listed as Principal Engineer at Western Digital.
What is Mark Mercado's email address?
AeroLeads has found 1 work email signal at @hgst.com for Mark Mercado at Western Digital.
What is Mark Mercado's phone number?
AeroLeads has found 1 phone signal(s) with area code 312 for Mark Mercado at Western Digital.
Where is Mark Mercado based?
Mark Mercado is based in San Francisco Bay Area, United States while working with Western Digital.
What companies has Mark Mercado worked for?
Mark Mercado has worked for Western Digital, University Of California, Santa Cruz, Hgst, Hitachi, and Ibm.
Who are Mark Mercado's colleagues at Western Digital?
Mark Mercado's colleagues at Western Digital include Siriluk Pichayaanankul, Tharika Chienarom, Robert Briner, Mohd Iqbal Alias, and Brian Young.
How can I contact Mark Mercado?
You can use AeroLeads to view verified contact signals for Mark Mercado at Western Digital, including work email, phone, and LinkedIn data when available.
What schools did Mark Mercado attend?
Mark Mercado holds Master Of Science (M.S.), Mechanical Engineering from Stanford University.
What skills is Mark Mercado known for?
Mark Mercado is listed with skills including Program Management, Design Of Experiments, Integration, Thin Film Development, Manufacturing, Enterprise Software, Thin Films, and Characterization.
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