AeroLeads people directory · profile
Matthew French Email & Phone Number
Sr. FPGA and ASIC Engineer
at
SpaceX
1 work email found
@spacex.com
LinkedIn matched
✓ Verified Jun 2026
4 data sources
Profile completeness 100%
Current company
Role
Sr. FPGA and ASIC Engineer
Location
Greater Seattle Area, United States, United States
Company size
Who is Matthew French? Overview
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Quick answer
Matthew French is listed as Sr. FPGA and ASIC Engineer at SpaceX, a company with 16865 employees, based in Greater Seattle Area, United States, United States. AeroLeads shows a work email signal at spacex.com and a matched LinkedIn profile for Matthew French.
Matthew French previously worked as FPGA & ASIC Engineer II at Spacex and FPGA & ASIC Engineer at Spacex. Matthew French holds Master Of Science - Ms, Electrical And Computer Engineering (Embedded Systems) from University Of Michigan.
Company email context
Email format at SpaceX
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{first}.{last}@spacex.com
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AeroLeads found 1 current-domain work email signal for Matthew French. Compare company email patterns before reaching out.
Profile bio
About Matthew French
I received my bachelor’s in computer engineering and master's electrical and computer engineering (major area: embedded systems) at the University of Michigan. I have experience designing and verifying ASICs and FPGAs as well as embedded systems. I love to explore and work on difficult technological problems that make an impactful difference. I’m interested in (not limited to) space, consumer electronics, robotics, and embedded systems.
Listed skills include C++, Microcontrollers, People Management, Arduino, and 11 others.
Current workplace
Matthew French's current company
Company context helps verify the profile and gives searchers a useful next step.
Spacex
9 roles
Matthew French work experience
A career timeline built from the work history available for this profile.
Fpga & Asic Engineer Ii
Current
Nov 2022 - Present
Fpga & Asic Engineer
Jan 2022 - Nov 2022
Fpga & Asic Rtl Design Intern
Parameterized existing RTL to efficiently instantiate RAM within a block, thereby reducing space and complexity throughout the top level. Proposed two novel packet generation and checker blocks after drawing block diagrams, writing documentation in reStructuredText, creating register files using SystemRDL, and receiving feedback from other team members..
May 2021 - Aug 2021
Fpga & Asic Design Verification Intern
Architected block-level UVM testbench in SystemVerilog to verify SpaceX IP block with 100% functional and code coverage. Diagnosed several issues during design verification process and worked closely alongside designer to resolve them before ASIC tape-out. Supplemented components to existing system-level UVM testbench to further verify untested.
May 2020 - Jul 2020
Hardware Systems Lead Engineer
Coordinated team of 10 engineers in iterative development of autonomous RC plane embedded system. Surveyed and procured system components to enable payload drop of unmanned ground vehicle, autonomous waypoint navigation, imaging object recognition, obstacle avoidance, and multiple communication links. Reduced battery weight by 12% by building custom.
Sep 2018 - May 2020
Computer Engineering Intern
Independently researched, designed, implemented, and tested standalone camera streaming server plugin for Unreal Engine 4 which provides high quality (1080p), low latency (8-10ms) video feeds of in-game imagery via RTSP to local network clients. Leveraged Nvidia’s GPU accelerated NVENC encoder by means of a hardware accelerator API to compress video feeds.
May 2019 - Sep 2019
Shift Lead
Organized and positioned team members, tracked inventory, delivered quality customer service, mediated disputes, and facilitated cashier cash handling.
Jun 2018 - Aug 2018
Intern
Worked in Sensing and Interaction Laboratory (SAIL). Researched and tested an IoT system comprised of microcontrollers, various sensors, server architecture, and an end-user mobile application. Verified limitations of system with many sensors and microcontrollers to evaluate course of future development plan.
Jun 2016 - Aug 2016
Team & coworkers
Colleagues at SpaceX
Other employees you can reach at spacex.com. View company contacts for 16865 employees →
ET
Erik Thompson
Colleague at SpacexGreater Seattle Area, United States, United States
View →
JQ
Jim Quattrochi
Colleague at SpacexPort Isabel, Texas, United States, United States
View →
JV
Javier Vega
Colleague at SpacexBrownsville, Texas, United States, United States
View →
KD
Kaitlin Devane
Colleague at SpacexLos Angeles, California, United States, United States
View →
AP
Alen Pelechatz
Colleague at SpacexTitusville, Florida, United States, United States
View →
WB
Westley Burlee E.I.T
Colleague at SpacexBrownsville, Texas, United States, United States
View →
KB
Karl Burnett
Colleague at SpacexCape Canaveral, Florida, United States, United States
View →
SR
Sieng, Reth
Colleague at SpacexWestminster, California, United States, United States
View →
AB
Asif Bashir
Colleague at SpacexRedmond, Washington, United States, United States
View →
AK
Aidan Kenjiro Mora
Colleague at SpacexParamount, California, United States, United States
View →
Erik Thompson
Colleague at SpacexGreater Seattle Area, United States, United States
View →
JQ
Jim Quattrochi
Colleague at SpacexPort Isabel, Texas, United States, United States
View →
JV
Javier Vega
Colleague at SpacexBrownsville, Texas, United States, United States
View →
KD
Kaitlin Devane
Colleague at SpacexLos Angeles, California, United States, United States
View →
AP
Alen Pelechatz
Colleague at SpacexTitusville, Florida, United States, United States
View →
WB
Westley Burlee E.I.T
Colleague at SpacexBrownsville, Texas, United States, United States
View →
KB
Karl Burnett
Colleague at SpacexCape Canaveral, Florida, United States, United States
View →
SR
Sieng, Reth
Colleague at SpacexWestminster, California, United States, United States
View →
AB
Asif Bashir
Colleague at SpacexRedmond, Washington, United States, United States
View →
AK
Aidan Kenjiro Mora
Colleague at SpacexParamount, California, United States, United States
View →
3 education records
Matthew French education
Master Of Science - Ms, Electrical And Computer Engineering (Embedded Systems)
University Of Michigan
Bachelor Of Science In Engineering - Bse, Computer Engineering, Minor Mathematics
University Of Michigan
Education record
Saint Ignatius High School
FAQ
Frequently asked questions about Matthew French
Quick answers generated from the profile data available on this page.
What company does Matthew French work for?
Matthew French works for SpaceX.
What is Matthew French's role at SpaceX?
Matthew French is listed as Sr. FPGA and ASIC Engineer at SpaceX.
What is Matthew French's email address?
AeroLeads has found 1 work email signal at @spacex.com for Matthew French at SpaceX.
Where is Matthew French based?
Matthew French is based in Greater Seattle Area, United States, United States while working with SpaceX.
What companies has Matthew French worked for?
Matthew French has worked for Spacex, M-Fly Aero Design, Dcs Corp, Kfc, and Case Western Reserve University.
Who are Matthew French's colleagues at SpaceX?
Matthew French's colleagues at SpaceX include Erik Thompson, Jim Quattrochi, Javier Vega, Kaitlin Devane, and Alen Pelechatz.
How can I contact Matthew French?
You can use AeroLeads to view verified contact signals for Matthew French at SpaceX, including work email, phone, and LinkedIn data when available.
What schools did Matthew French attend?
Matthew French holds Master Of Science - Ms, Electrical And Computer Engineering (Embedded Systems) from University Of Michigan.
What skills is Matthew French known for?
Matthew French is listed with skills including C++, Microcontrollers, People Management, Arduino, Team Leadership, Sensors, Computer Hardware, and Time And Attendance.
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