Matthew French Email & Phone Number

Kirkland, Wa, Us

Hawthorne, California, Us

Hawthorne, California, Us

Hawthorne, California, Us

Parameterized existing RTL to efficiently instantiate RAM within a block, thereby reducing space and complexity throughout the top level. Proposed two novel packet generation and checker blocks after drawing block diagrams, writing documentation in reStructuredText, creating register files using SystemRDL, and receiving feedback from other team members. Developed efficient RTL in Verilog to implement proposed designs and further optimized design to close timing with a 500 MHz clock. Performed full FPGA build with integrated blocks to validate design on real hardware

Hawthorne, California, Us

Architected block-level UVM testbench in SystemVerilog to verify SpaceX IP block with 100% functional and code coverage. Diagnosed several issues during design verification process and worked closely alongside designer to resolve them before ASIC tape-out. Supplemented components to existing system-level UVM testbench to further verify untested functionality. Initialized foundations for testbench to verify RISC-V core implementation using random assembly instruction generation

Ann Arbor, Us

Coordinated team of 10 engineers in iterative development of autonomous RC plane embedded system. Surveyed and procured system components to enable payload drop of unmanned ground vehicle, autonomous waypoint navigation, imaging object recognition, obstacle avoidance, and multiple communication links. Reduced battery weight by 12% by building custom monitoring hardware and logging power usage to determine optimal specification. Illustrated line diagram and soldered efficient wiring harness for plug-and-play modular design and minimization of weight. Implemented safety workaround for flying manually by routing flight servo controls into custom switching mechanism PCB

Alexandria, Va, Us

Independently researched, designed, implemented, and tested standalone camera streaming server plugin for Unreal Engine 4 which provides high quality (1080p), low latency (8-10ms) video feeds of in-game imagery via RTSP to local network clients. Leveraged Nvidia’s GPU accelerated NVENC encoder by means of a hardware accelerator API to compress video feeds into h.264 format for efficient streaming thereby removing significant dependency on CPU

Dallas, Tx, Us

Organized and positioned team members, tracked inventory, delivered quality customer service, mediated disputes, and facilitated cashier cash handling.

Cleveland, Oh, Us

Worked in Sensing and Interaction Laboratory (SAIL). Researched and tested an IoT system comprised of microcontrollers, various sensors, server architecture, and an end-user mobile application. Verified limitations of system with many sensors and microcontrollers to evaluate course of future development plan.

Master Of Science - Ms, Electrical And Computer Engineering (Embedded Systems)

Bachelor Of Science In Engineering - Bse, Computer Engineering, Minor Mathematics

Education record