Scott Mccann Email & Phone Number

The Packaging R&D group in Xilinx was responsible for the development of all packaging technology, from early identification of which technologies to pursue and product design and development through qualification. As a fabless company, we relied on our fabs and vendors and maintained critical relationships with them. I focused on test vehicle development and demonstration and fundamental thermal-mechanical aspects at the package level.• Led high-density fan-out package for single die from development to product launch and supporting bring up of new product flow for high-density fan-out package platform to enable FPGAs in form-factor constrained markets. Responsibilities: build creation, build tracking, component level reliability, design rules, documentation, failure analysis, qualification ownership, process flow, technical issue tracking and resolution, test hardware readiness, and board level reliability.• Co-led an industry leading 65mm stacked silicon interconnect technology (aka 2.5D silicon interposer) package, the largest FPGA ever circa 2019, from test vehicle conception to product launch.• Developed modeling methodology for industry leading stacked silicon interconnect FPGA and monolithic packages to predict warpage, coplanarity, top die stress, µbump and first level underfill stress, C4 and second level underfill stress, board level thermal cycling, and monotonic bend.• Led board level reliability work including thermal cycling, bend, shock, and vibration for multiple test vehicles. Demonstrated significant improvement in performance by and developed guidelines to support customer application of edge bonding.• Lead technical author (2017-2018) and editor (2019-present) of Xilinx’s Thermal and Mechanical Guidelines for Lidless FPGA Packages.• Represented Xilinx at JEDEC committee meetings and added 0.92mm BGA pitch for large BGA packages.

Atlanta, Georgia, United States

The research was funded by the Low-cost Glass Interposer Program at PRC, focusing on the development of glass substrates and interposer packaging. The work involved semi-annual industry advisory board review meetings, quarterly reports, monthly webinars, and one-on-one phone calls with industry mentors. Delivered on-time and to-quality for my research tasks, transferred the knowledge through presentation and written reports to industry partners, and successfully implemented the design guidelines for future packages.• Developed and demonstrated design guidelines for ultra-thin (100μm) 2.5D glass packages to prevent core cracking due to dicing-induced defects and RDL stresses which relate the maximum build-up thickness based on dicing method and process variations, such as pull back and edge coating.• Developed novel finite element models for applications including ultra-thin glass substrate cracking, thermo-compression process development, and sequential package warpage during fabrication. Validated models using shadow moiré measurement, fracture tests, and other experimental techniques.• Supported consortium demonstrator test vehicles including 2.5D high performance, mobile, fan-out, and high temperature as well as fundamental research projects including copper-copper interconnects, thermo-compression process development, metastable solid-liquid interdiffusion (aka transient liquid phase) bonding, and cohesive zone modeling development and characterization.

• Teaching assistant for the graduate level finite element method course designed, including giving lectures. Course taught an in depth understanding of theory behind finite element method and expertise in handling commercial software tools, such as ANSYS®.• Taught lab sessions to impart fundamental principles to successfully build reliable finite-element models on fundamental mechanical topics, give students practical experience with ANSYS®, and give an overview finite-element modeling of assembly characterization and reliability tests with an interdisciplinary approach.

Chandler, Arizona, United States

• Developed method to determine thermal conductivity through transient temperature data.• Managed year-long DOE to investigate degradation of thermal interface material during power cycling.• Continued development of customer facing, web-based, thermal design and modeling system.• Characterized strengths of solder using tension and double lap shear tests; data was used to develop fatigue life prediction models and analyzed failure modes.

Doctor Of Philosophy - Phd, Mechanical Engineering

Major: Mechanics of Materials Minor: Microelectronic Packaging

Master Of Science - Ms, Mechanical Engineering

Bachelor Of Science - Bs, Mechanical Engineering