Michael Low Email & Phone Number

-Senior Analog IC Design Engineer for Consumer, Automotive, Medical, and Military Industry.-Issued 9 US Patents and 1 pending related to systems, optical, and semiconductors.-I create designs, simulations and layouts using Cadence, Mentor and Tanner EDA, including DRC, ERC, LVS, and PEX.-System and Circuit Design (analog and digital) using CMOS, BiCMOS, and Bipolar technology (28 nm - 1 micron).-Designing includes specification, architecture, transistor level, layout, chip debug, verification, and lab validation and documentation.-Cells include power on reset, bandgap, comparator, low noise op amp, buffers, low input leakage op amp, LVDS input and output, CML output, DDR output, ADC, DAC, PLL, level shifter, ESD, voltage regulator, and clamps.Specialties: Customer interface, product definition, application block diagrams, specification generation, technology selection, die size estimates, packaging, cost analysis, circuit design, floor planning, layout, evaluation, test generation, failure analysis, documentation, and production release.

Listed skills include Ic, Circuit Design, Asic, Analog, and 33 others.

• 

  Ic Design Engineer

  Sri International

  Apr 2020 - Present - Princeton, New Jersey, United States

  IC Design Engineer for Micro Electronics Center.